JPH0525331B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention is a dynamic RAM controller that generates at least two types of row address strobe signals and two types of column address strobe signals in response to a byte/word selection signal to select a predetermined memory block. A plurality of memory blocks can be accessed singly or simultaneously by supplying a plurality of memory blocks.

[Industrial application field]

The present invention relates to a dynamic RAM controller that separates addresses supplied from a CPU into row addresses and column addresses and dynamically dynamically processes them in chronological order.
Regarding the dynamic RAM controller that supplies RAM.

In dynamic RAM, memory cells are arranged in a matrix at the intersections of orthogonal word lines and bit lines, and by specifying an arbitrary word line with a row address, information on all memory cells connected to this word line is detected. Then, a single memory cell is accessed by specifying an arbitrary bit line using a column address.

Therefore, after detecting the information of all memory cells connected to a given word line, it is possible to access multiple memory cells at high speed by fixing the row address and sequentially changing the column address. .

This high-speed access mode includes two modes: nibble mode, in which the row address is fixed and the column address is incremented four times to sequentially access memory cells at four consecutive column addresses, and the other is nibble mode, in which the row address is fixed and the column address is arbitrary. There is a page mode in which memory cells at multiple column addresses are accessed sequentially.

In addition, since it takes about 100 msec to precharge the word lines of dynamic RAM, dynamic RAM is divided into multiple memory banks (memory blocks), and when data from a single bank is read, data from other banks is By performing precharging, the access speed of dynamic RAM is apparently increased (memory interleaving).

[Conventional technology]

FIG. 6 shows a block diagram of a system using a conventional dynamic RAM controller. In the figure, the CPU 10 includes an external timing signal generation circuit, etc., and includes a dynamic RAM.
(hereinafter referred to as "D-RAM") A strobe signal that generates an address for accessing the section 11 and instructs the timing of fetching a row address.
It generates RAS, strobe signals that instruct column address capture timing, and various control signals.

the above address and strobe signals,
The CAS and control signals are each supplied to the dynamic RAM controller 12. The dynamic RAM controller 12 separates addresses into row addresses and column addresses and supplies them to the D-RAM section 11 in time series, and also supplies row address strobe signals 0 to 3, column address strobe signals,
Generates a write enable signal and writes D-RAM
11.

The strobe signals 0 to 3 above are CPU
Either one is generated by decoding two bits of the address supplied from 10 inside the controller.

The D-RAM section 11 has a four-bank configuration consisting of memory banks 11a to 11d, each of which performs input/output in units of 16 bits, and receives row addresses, column addresses, column address strobe signals, and write enable signals from the dynamic RAM controller 12. These memory banks 11a~
11d, row address strobe signals 0-3 are commonly supplied to memory banks 11a-1.
1d separately. As a result, the row address and column address are taken in and accessed in the memory bank to which both the row address strobe signal and the column address strobe signal are supplied among the memory banks 11a to 11d. Each of the memory banks 11a to 11d has a 16-bit data bus 13.
It is connected to the CPU 10 via.

[Problem that the invention seeks to solve]

For example, Intel's 8086, Motorola's
A CPU such as the 68000 outputs a byte/word selection signal that selects whether to access the memory in byte units or in word (=2 byte) units.

However, conventional dynamic RAM controllers do not use the above-mentioned byte/word selection signals, and can only select a single bank and perform word access as shown in FIG.
There was a problem that the functions of the system were not fully utilized.

The present invention has been made in view of the above points, and an object of the present invention is to provide a dynamic RAM controller that can access a plurality of memory banks, one or more at the same time.

[Means for solving problems]

The dynamic RAM controller of the present invention is
A row address strobe that is supplied with a memory access request signal and a clock signal with a higher frequency than the system clock signal used by the CPU, takes in the memory access request signal using the clock signal, and instructs to take in a row address synchronized with the clock signal. A column address strobe signal that instructs the capture of a column address is generated after a fixed time delay after the generation of a row address signal.
In the high-speed access mode of the RAM section, after generating a column address strobe signal, a column address strobe signal for the high-speed access mode is generated in synchronization with the clock signal to select between byte access and word access supplied by the CPU 20. Depending on the designated byte/word selection signal, a row address strobe signal and a column address strobe signal themselves or at least two types of row address strobe signal and column address strobe signal without a capture instruction are generated, and a plurality of memory blocks A predetermined row address strobe signal and a column address strobe signal of at least two types of row address strobe signals are supplied to each of the row address strobe signals.

That is, for example, if we consider a case where a plurality of memory blocks are arranged in a matrix, the same row address strobe signal is supplied to each of the plurality of memory blocks arranged in the row direction, and the same row address strobe signal is supplied to the plurality of memory blocks arranged in the column direction. The same column address strobe signal is applied to each of the memory blocks, and the combination of the row address strobe signal and the column address strobe signal allows access to a desired memory block to which both row and column address strobe signals are applied simultaneously.

[Effect]

In the present invention, by simply generating a CPU address and a memory address request signal, a column address strobe signal for high-speed access mode is generated in synchronization with a clock having a higher frequency than the system clock, thereby enabling high-speed access. Also, part-time job/
In response to the word selection signal, a predetermined combination of a predetermined row address strobe signal and a column address strobe signal is supplied to each of the plurality of memory blocks 29a to 29d. A plurality of memory blocks 29a~
The row address strobe signal and column address strobe signal supplied to 29d are either in the capture instruction or no capture instruction generated from the memory access request signal, and address both the row and column according to the combinations described above. Since only memory accesses in which both strobe signals are in the capture instruction state are accessed, multiple memory blocks 29a to 29a are accessed.
29d can be accessed single or multiple times at the same time.

〔Example〕

FIG. 1 shows an overall configuration diagram of a system using the dynamic RAM controller of the present invention.

In the figure, 20 is a CPU, which operates by being supplied with a system clock signal of several MHz from a clock generator 21, and sends each 10-bit row address and column address to address buses 22a and 22b.
address strobe signal as a memory access request signal that instructs address capture timing, read/write signal R/ that switches between reading and writing, bank select signal BS that instructs upper bank and lower bank, and byte access and Byte/word selection signals BAC0, BAC to instruct word access
1. Outputs a control signal for instructing nibble mode in high-speed access mode, a control signal for instructing page mode in high-speed access mode, and an external/internal refresh switching signal. This bank select signal BS is one bit in the address, and the control signal is output using an empty bit in the address.

The dynamic RAM controller 23 is composed of a multiplexer 24, a refresh time generator 25, an arbiter 26, and a timing generator 27.

The multiplexer 24 connects the address buses 22a, 2
Either the row address or the column address supplied from 2b is switched and selected according to the selection signal, and the selected one is supplied to the D-RAM section 29 from the address bus 28.

When the external/internal refresh switching signal indicates the internal refresh mode, the refresh time generator 25 generates a refresh request signal that requests refreshing of the D-RAM 29 at a constant cycle from the clock signal CLK supplied from the clock generator 21. is generated and supplied to the arbiter 26. By the way, the clock signal CLK outputted from the clock generator 21 is a source oscillation signal and has a frequency several times that of the system clock signal, for example, 15 to 30 MHz.

The arbiter 26 operates in synchronization with the clock signal CLK, is supplied with the refresh request signal and the address strobe signal, determines and adjusts the priority of the read/write cycle and the refresh cycle, and outputs the adjusted refresh cycle. The load request signal is supplied to the timing generator 27.

The timing generator 27 receives the above-mentioned refresh request signal, address strobe signal from the CPU 20, and read/write signal R/
W, bank select signal BS, byte/word selection signals BAC0, BAC1, control signal,
and the clock signal CLK, a selection signal instructing selection of switching between row address and column address is generated and supplied to multiplexer 24, and row address strobe signals 0, 0,
1, row address strobe signal 0, 1,
Generate each write enable signal and
It supplies it to the RAM 29, and also generates a ready signal RDY indicating that it is a refresh cycle and supplies it to the CPU 20.

The main parts of the timing generator 27 mentioned above will be explained in more detail with reference to FIG.

In the figure, a refresh request signal that is at H level in a read/write cycle and goes to L level when a refresh cycle is required is input to terminal 31, and an address input signal is input to terminal 32 at L level. Address strobe signal that directs
AS is input, and a clock signal CLK is input to terminal 33. Further, a control signal of H level in normal access mode and L level only in nibble mode in high speed access mode is input to terminal 34.
A control signal is input to the terminal 35 at an H level in the normal access mode and at an L level only in the page mode in the high speed access mode.

Since the refresh request signal is at H level in the read/write cycle, the address strobe signal AS shown in FIG. . Also,
The address strobe signal is inverted by an inverter 38 and supplied to the P terminals (preset terminals) of flip-flops 37 and 39, respectively.
The operation is performed after AS becomes L level. The clock signal CLK shown in FIG. 3A is connected to the buffer amplifier 4.
After passing through 0, the signal is supplied to the CLK terminal of flip-flop 39, and is also supplied to the CLK terminal of flip-flop 37 via inverter 41.

After the address strobe signal AS goes low, the flip-flop 37 outputs the clock signal CLK.
At the fall of the first pulse _P1 , the Q terminal output is set to L level. The D-type flip-flop 39 whose D terminal is supplied with this Q terminal output outputs the second pulse P ₂
At the rising edge of , the output of the flip-flop 37 is taken in and the Q terminal output is set to L level. The Q terminal output of this flip-flop 39 is the buffer amplifier 42.
a, 42b, respectively, and the terminal 43a or 43
b is output as a row address strobe signal 0 or 1 as shown in FIG. 3C.

Incidentally, the delay time _t1 for the fall of the strobe signal 0 or 1 is due to the flip-flop 39 and the buffer amplifiers 40 and 42.

The Q terminal output of the flip-flop 39 is delayed for a certain period of time by a delay circuit 44 and then transferred to an inverter 45.
The signal is inverted and supplied to the NAND circuit 46. Since the counter 47 that supplies the signal to the NAND circuit 46 outputs an H level when the address strobe signal becomes L level, the output signal of the inverter 45 is inverted by the NAND circuit 46, and is further inverted by the buffer amplifier 48a. , 48b, respectively, and a column address strobe signal 0 or 0 as shown in FIG.
Output as CAS1. Here, the delay circuit 44
The delay time _t2 is the sum of the row address hold time _t3 and the column address setup time _t4 shown in FIG. 4F.

Furthermore, the Q terminal output of the flip-flop 39 is processed by the row address hold time t ₃ in the delay circuit 50.
After being delayed by 10 minutes, the signal is supplied from terminal 51 to multiplexer 24 as a selection signal.

The operation up to this point is the same in both normal access mode and high-speed access mode. In normal access mode, after the address strobe signal rises, the strobe signal 0 or 1
and 0 or 1 rises. This is because the address strobe signal is inverted and supplied to the P terminal of flip-flop 39, and when the address strobe signal goes to H level, flip-flop 39 is preset and its Q terminal output goes to H level.

The decoder 54 is supplied with control signals from the terminals 34 and 35 via inverters 52 and 53, respectively, and supplies an H level signal to the AND circuit 55 only in the high speed access mode. It also generates 2-bit control signals for instructing each of the high-speed access modes, nibble mode and page mode, and supplies them to the counter 47.

The AND circuit 55 supplies the clock signal CLK to the CLK terminal of the counter 47 only when a high-speed access mode is requested.

The counter 47 is supplied with an address strobe signal to its R terminal, and this address strobe signal
It is reset at the falling edge of AS and outputs an H level signal. In addition, a flip-flop 39 is connected to the EN terminal of the counter 47 via an inverter 56.
The Q terminal output of is supplied, and the strobe signal
After RAS0 or RAS1 goes low, the counter 47 starts counting the clock signal CLK. That is, counting starts from the third pulse of the clock signal CKL in FIG. 3A, and after detecting the rise of the sixth pulse _P6 after four pulses, the seventh pulse
An L level signal is output until the rising edge of _P7 is detected, and then a signal whose L level period corresponds to approximately two pulse periods of the clock signal CLK is generated and output at three pulse periods of the clock signal CLK. As shown in FIG. 3E, when the control signal is at the L level and the control signal from the decoder 54 instructs the nibble mode, the counter 47 generates an L level signal four times, and after reaching the L level at the fourth time, the counter 47 generates an L level signal four times. This L level is maintained. In the page mode, the generation of the L level signal is repeated every three clock cycles of the clock signal CLK. The counter 47 and the circuits from inverter 52 to inverter 56 constitute a high-speed access column address strobe generation circuit 61.

The output signal of this counter 47 is the NAND circuit 46
and when the NAND circuit 46 receives the L level signal from the counter 47, it outputs the strobe signal.
Set CAS0 or 1 to H level. This allows the strobe signal to be 0 or 0 in nibble mode.
CAS1 is as shown in Figure 3D.

A bank select signal BS, whose H level indicates the upper bank and whose L level indicates the lower bank, is input to the terminal 60. Byte/word selection signals BAC0 and BAC1 are input to terminals 61 and 62, both of which are at L level to instruct word access, and only one of which is at H level to instruct byte access.

The signals as shown in FIG.
supplied to When the Q terminal output of the flip-flop 39 falls, the decoder 63 outputs the bank select signal BS and the byte/word select signal.
Latch BAC0 and BAC1 respectively. After this, the latched signal is decoded and the buffer control signal is
Generate BC1 to BC4, buffer amplifier 42a,
It is supplied to each control terminal of 42b, 48a, and 48b separately.

Buffer amplifiers 42a, 42b, 48a, 48
b are strobe signals 0, 1, and 1, respectively, according to the buffer control signals BC1 to BC4 described above.
0 and 1 respectively to terminals 43a, 43b, 49a,
49b, respectively.

FIG. 4 shows the relationship between the bank select signal BS, byte/word select signals BAC0, BAC1, and strobe signals 0, 1, 0, 1, respectively. In the figure, bank select signal
BS, byte/word selection signal BAC0, BAC1
The H level is represented by "1" and the L level is represented by "0". Also, strobe signal 0,
1, 0, and 1 are respectively output as "valid", and "H" indicates that terminals 43a, 43b, 49a, and 49b are output at a fixed H level. . As a result, in mode numbers 1 and 2, two memory banks are selected for word access, in mode numbers 3 to 6, a single memory bank is selected and byte access is performed, and in mode number 7, a single memory bank is selected for byte access. Four memory banks are selected and longword access, which is 4-byte batch access, is performed, and in mode number 8, no memory bank is accessed.

Returning to FIG. 1, multiplexer 2
4 performs address switching and selection by the signal supplied from the terminal 51 in FIG. 2. In the nibble mode, as shown in FIG. bus 28
Send to.

The D-RAM section 29 is composed of four memory blocks, ie, memory banks 29a to 29d. Each of these memory banks 29a to 29d is composed of eight dynamic RAM elements and performs input/output in units of 8 bits. It is something.

The row address and column address from the address bus 28 are supplied to all memory banks 29a to 29d.
In addition, the write enable signal output from the timing generator 27 is also applied to all memory banks 29a.
~29d. strobe signal 0
is supplied to memory banks 29a and 29b, and strobe signal 1 is supplied to memory banks 29c and 29b.
d. Furthermore, strobe signal 0 is supplied to memory banks 29a and 29b, and strobe signal 0 is supplied to memory banks 29c and 29d.
supplied to That is, for example, considering a case where a plurality of memory blocks 29a to 29d are arranged in a matrix, the same row address strobe signals 0 and 1 are applied to the plurality of memory blocks 29a and 29b, 29c and 29d arranged in the row direction, respectively.
and the same column address strobe signals 0, 29c, 29b, and 29d arranged in the column direction.
1 respectively, and the row address strobe signal
RAS0, 1 and column address strobe signal
The combination of CAS0 and CAS1 allows access to a desired memory block to which both row and column address strobe signals are supplied simultaneously.

Further, memory banks 29a and 29c are connected to the upper 8 bits of a 16-bit data bus 30, and memory banks 29b and 29d are connected to the lower 8 bits of the data bus 30. This data bus 3
All 0 bits are connected to the CPU 20.

Therefore, in mode number 1 shown in FIG. 4, the row address and column address are taken into the memory banks 29a and 29b and accessed simultaneously, thereby performing word access. In mode number 2, memory banks 29c and 29d are word-accessed simultaneously.

In mode number 3, the row address and column address are taken only into the memory bank 29d and byte access is performed, and in the same way, in mode numbers 4, 5,
6 respectively, memory banks 29c, 29a, 29b
Each byte is accessed separately. In mode number 7, row addresses and column addresses are taken into all memory banks 29a-29d, so that they are used when data bus 30 is 32 bits and long word access is performed. In mode number 8, row addresses and column addresses are not taken into all memory accesses 29a to 29d, so they are not used when using one of the D-RAM sections in a system in which two sets of D-RAM sections 29 are connected. D-
It can be used in place of the chip select signal for the RAM section.

Note that the case of mode number 5 in the normal access mode will be explained in detail.

Strobe signals 0 and 0 shown in FIGS. 5A and 5B are supplied to the memory bank 29a, row addresses and column addresses are taken in, and byte access is performed. Strobe signals 0 and 1 shown in FIG. 5C and D are supplied to the memory bank 29b, and since the strobe signal 1 maintains the H level, the memory bank 29b is refreshed (RAS only refresh). The memory block 29c is supplied with strobe signals 1 and 0 shown in FIG. 5E and F, and the memory block 29d is supplied with strobe signals 1 and 1 shown in FIG. 5G and H, and the strobe signal 1 is set to H. In order to maintain the level, memory blocks 29c and 29d are not accessed.

In this way, byte/word selection signals BAC0,
Strobe signal 0 according to BAC1,
Since 1, 0, 1 is generated, the memory banks 29a to 29d are sent as a byte/word selection signal.
Byte access or word access can be performed depending on BAC0 and BAC1.

Furthermore, since the strobe signals 0, 1, 0, 1 are generated in response to the bank select signal BS, only a single memory bank among the four memory banks 29a to 29d can be accessed during byte access.

As a result, the
The byte/word selection function of the CPU 20 can be utilized.

Note that the memory banks 29a to 29d may be configured to perform input/output in units of 1 word (16 bits). In this case, the byte/word selection signal
When BAC0 and BAC1 instruct byte access, word access to a single memory bank 29a is performed, and byte/word selection signals BAC0 and
When BAC1 instructs word access, two memory banks are accessed simultaneously to perform longword access.

〔Effect of the invention〕

As described above, according to the dynamic RAM controller of the present invention, high-speed access is possible by generating a column address strobe for high-speed access mode using a clock with a higher frequency than the CPU's system clock, and bytes/words output by the CPU. A plurality of memory blocks can be accessed singly or simultaneously in response to a selection signal, and the byte/word selection function of the CPU can be fully utilized, which is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of a system using the dynamic RAM controller of the present invention.
FIG. 2 is a circuit configuration diagram of an embodiment of the main part of the timing generator shown in FIG. 1, FIG. 3 is a signal time chart of each part of the circuit shown in FIG.
A diagram for explaining the relationship between the illustrated CPU output signal and the dynamic RAM controller output signal, FIG. 5 is a signal time chart of the strobe signal of each memory bank, and FIG. 6 is a block configuration diagram of an example of a conventional system. . In the figure, 20 is a CPU, 21 is a clock generator, 23 is a dynamic RAM controller, 24 is a multiplexer, 25 is a refresh time generator, 26 is an arbiter,
27 is a timing generator, 29 is a dynamic RAM (D-RAM) section, 29a to 29d are memory banks, 42a, 42b, 48a, 48b
is a buffer amplifier, and 63 is a decoder.

Claims (1)

[Claims] 1. The CPU 20 is supplied with an address for accessing the dynamic RAM unit 29 and a memory access request signal instructing to take in the address,
separating the address into a row address and a column address, and generating a row address strobe signal instructing to take in the row address and a column address strobe signal instructing to take in the column address from the memory access request signal; The row address, column address, row address strobe signal, and column address strobe signal are transmitted to the dynamic RAM section 2.
A dynamic RAM controller 23 supplies a plurality of memory blocks constituting the CPU 20, and is supplied with the memory access request signal and a clock signal with a higher frequency than the system clock signal used in the CPU 20, and is supplied with the memory access request signal and a clock signal with a higher frequency than the system clock signal used in the CPU 20. generates a row address strobe signal that instructs to take in the row address in synchronization with the clock signal, and instructs to take in the column address after a fixed time delay after generation of the row address signal. Generates a column address strobe signal, and after generating the column address strobe signal during the high-speed access mode of the dynamic RAM section,
A column address strobe signal for high-speed access mode is generated in synchronization with the clock signal, and the row address strobe signal is generated in response to a byte/word selection signal supplied from the CPU 20 that instructs selection between byte access and word access. A signal and a column address strobe signal itself or at least two types of row address strobe signals and a column address strobe signal without a capture instruction are generated, and the at least two types of row address strobe signals and a column address strobe signal are respectively transmitted to the plurality of memory blocks. A dynamic RAM controller configured to supply a predetermined row address strobe signal and a column address strobe signal of the column address strobe signal.