KR890008560Y1 - Timing generator of dram - Google Patents

Abstract

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Description

DRAM Timing Generator

1 is a configuration diagram of a memory system using a DRAM timing generator according to the present invention.

2 is a DRAM timing generator circuit diagram of the present invention.

The present invention relates to a DRAM (Dynamic RAM) timing generator in a memory system of a computer.

In the conventional PC system memory, four input switches were allocated to configure 640KB of memory in units of 64K bytes. Therefore, a separate switch was required to have individuality of each PC system, and memory expansion was performed through a slot. There was an uncomfortable fault.

Accordingly, an object of the present invention is to provide a memory timing generator capable of stepwise controlling a memory of 256KB, 512KB and 640KB having the most useful memory system by using two input switches.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram of a memory system using a DRAM timing generator of the present invention, wherein 10 is an address multiplexer, 20, 21, and 22 are two 256KB DRAMs and one 128KB DRAM, and 30 is a DRAM timing generator.

In the drawing, the address multiplexer 10 which multiplexes the addresses AD ₀ -AD ₁₇ applied through the address bus of the main system includes the multiplexed 8-bit addresses MA ₀ -MA ₈ in the DRAM banks 20, 21. , The DRAM timing generator 30 for applying the switch signals SW ₁ and SW ₂ and the addresses AD _{17 to} AD ₁₉ for determining the size of the memory. A pair of row address write signals (RAS), which are a row address write signal, and a column address strobe (CAS), an open-write write signal, are respectively applied to the DRAM bank to store or output data.

2 is a circuit diagram of the DRAM timing generator.

In the drawing, the switch signals SW ₁ and SW ₂ for determining the size of the memory are signals for determining the DRAM usage step by step as shown in Table 1 below by a combination of two switches on and off.

Therefore, the DRAM bank 20 is selected as the output signal of the NAND gate G ₃ , the DRAM bank 21 is selected as the NAND gate G ₄ , and the DRAM bank 22 is selected as the NAND gate G ₃ .

The OR gate G ₁ for ORing the switch signals SW ₁ and SW ₂ and the AND gate G ₂ for ANDing are also connected to the NAND gates G _{3 and} G ₅ , and to the NAND gate G ₄ . The switch signal SW ₁ is applied, and the output addresses AD ₁₇ -AD ₁₉ of the main system are directly applied to the NAND gates G ₃ -G ₅ through the inverting gates G ₆ -G ₈ , respectively, but the DRAM The logic diagram applied to the NAND gates G ₃ -G ₅ for selecting the banks (20-22 of FIG. 1) is shown in Table 2 below.

Thus NAND gate DRAM bank selection signal output from the (G ₃ -G ₅₎ are NAND gates (G ₉₎ is applied to a NAND gate (G ₉₎ output signal and the DMA (Direct Memory Acess) an acknowledge signal (DACK of The NAND getter G ₁₀ applying 0) outputs a RAM enable signal RAMEN.

That is, when DACK 0 is a logic "1" signal, it is time to write and read memory data. This signal is used to generate RAMEN.

Each output signal of the NAND gates G ₃ -G ₅ is applied to another input terminal of each NOR gate G ₁₁ -G ₁₃ to which the RAM enable signal is applied, and a memory device input buffer signal applied from the main system ( The output signal of the NAND gate G ₁₇ that applies the MEMWB and the memory read buffer signal MEMWB is logically multiplied by the DMA occlusion signal DACK 0 and the AND gate G ₂₀ passing through the inverted gate G ₁₈ . and is applied to one input terminal of each NOR gate (G ₁₄ -G _16), a NOR gate (G ₁₄ -G ₁₆₎ are each NOR gate the other input terminal (G ₁₁ -G ₁₃₎ be applied to each row of the output signal is Output the address write signal (RAS 0-RAS 2).

In other words, the NAND gate G ₁₉ outputs a logic “0” signal of the MEMWB or the MEMWB, so that the NOR gates G _11- G ₁₃ are in an active high state to selectively drive the corresponding DRAM banks.

Therefore, the NOR gates G ₁₄ -G ₁₆ output the row address write signal corresponding to each bank.

In addition, an output signal of the NAND gate G ₁₉ is an inverting gate G ₂₁ at another input terminal of the NAND gates G ₂₄ -G ₂₆ to which respective output signals of the NOR gates G ₁₁ -G ₁₃ are applied. As the input / output signal of the delay circuit DLY is multiplied by the AND gate G ₂₂ and applied thereto, a column address write signal CAS 0 -CAS 2 is applied to each output terminal of the NAND gates G ₂₄ -G ₂₆ . Outputs

In this way, the delay time signal of the delay circuit DLY is logically multiplied with the output inversion signal of the NAND gate G ₁₉ , and this ANDed signal is applied to the NAND gates G ₂₄ -G ₂₆ so that the column address start-up signal ( CAS 0-CAS 2) is output.

The other input / output signal of the delay circuit DLY is used as the RAM address selection signal RAMADSEL through the inversion gate G ₂₃ , which is used to delay the MEMWB or MEMRB to switch the row address and column addresser. Inverted signal.

On the other hand, when DACK 0 is a logic " 0 ", the DRAM is disabled and enters the leaf refresh mode to generate only the row address write signal RAS.

Therefore, using RAS 0-RAS 2 and CAS 0-CAS 2, only RAS 0 and CAS 0 operate when the memory capacity of the system is 256KB, and RAS 0-RAS 1 and CAS 0-CAS 1 operate when 512KB. RAS 0-RAS 2 and CAS 0-CAS 2 operate in the 640KB region.

As described above, according to the present invention, a two-stage 256KB, 512KB, and 640KB useful three-step memory system can be used step by step without using slots and can be applied to various types of computer systems. have.

Claims (1)

The AND gate G ₂ , which is the OR gate G ₁ that ORs the switch signals SW ₁ and SW ₂ , is connected to each NAND gate G ₃ and G ₅ , and the switch signal SW ₂ is NAND. The NAND gates G ₃ -G ₅ are connected to the gate G ₄ , and the NAD gates G _3- G ₅ are applied to the other input terminal in combination with the addresses AD _17- AD ₁₉ of the main system. The NAM gate (G ₉ ) output signal connected to the output and applying the DRAM bank selection signal and the RAM enable signal of the NAND gate (G ₉ ) applying the DAM acknowledgment signal are the DRAM bank selection signal and the NAND gate ( G ₁₉ ) The output signal is connected to the noah gates G ₁₁ -G ₁₃ , the NAND gate G ₁₇ for applying the memory write and read buffer signals of the main system, and the inverted gate for applying the DMA acknowledgment signal ( G ₁₈₎ output of the AND gate (G ₂₀₎ of the output signal of OR To a signal to be applied to an output terminal of each NOR gate (G ₁₁ -G ₁₃₎ connected to the other input terminal of the NOR gate (G ₁₄ -G ₁₆₎ for generating a row address write signal, DMA acknowledge signal and a delay circuit (DLY) The output signal of the NAND gate G ₁₉ , which applies the input signal of, is applied to the output signal of the delay circuit DLY and the AND gate G ₂₂ through the inversion gate G ₂₁ , and then output. The other input terminal of the NAND gates G ₂₄ -G ₂₆ generating the address write signal is connected to the output terminal of each NOR gate G ₁₁ -G ₁₃ , and the signal output through the other output terminal of the delay circuit DLY is inverted. And a DRAM timing generator connected via a gate (G ₂₃ ) for use as a RAM address selection signal.