JPH04319751A - Memory control system - Google Patents

Abstract

PURPOSE:To reduce the. number of memory chips and to reduce the size and space of this memory control system by sharing a parity module by four memory modules. CONSTITUTION:A memory circuit for executing parity check is provided with four memory modules 1 to 4, a parity module 5 for the four memory modules 1 to 4, multiplexers 13, 14 for forming row and column addresses consisting of the memory modules 1 to 4 and the parity module 5, and a decoder 15 for forming an enable signal for selecting one of accesses to the memory modules 1 to 4.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control system having a parity check function, and more particularly to a memory control system that can reduce the number of parity modules for parity data in a memory circuit having a plurality of memory modules.

0002

[Prior Art] Conventionally, this type of memory control method is shown in FIG.
As shown in FIG.
Parity modules 22, 23, 24, 25 composed of four 6k×1-bit memory chips, a multiplexer 13, a decoder 15, and OR gates 9, 10, 11
, 12, and the memory modules 1, 2, 3, and 4 and the parity modules 22, 23, 24, and 25 formed pairs.

0003

[Problems to be Solved by the Invention] The conventional memory control method described above requires one parity module for one memory module, so the number of memory chips used for parity check increases, making it difficult to The disadvantage is that it is not suitable for standardization.

An object of the present invention is to share one parity module with a plurality of memory modules.
It is an object of the present invention to provide a memory control method that can reduce the number of memory chips and achieve miniaturization and space saving.

[0005]

Means for Solving the Problems The present invention provides a memory control system that performs a parity check, which includes a memory module, and one parity module for storing parity data of the four memory modules, for each of the four memory modules. It is characterized by having a module.

Further, according to the present invention, a multiplexer for switching the row address and column address of the memory module and the parity module excluding the upper 1 bit, and a multiplexer for switching the row address and column address of the upper 16 bits of the parity module. Preferably, the memory module includes a multiplexer for switching access to the memory module, and a decoder for generating an enable signal for switching access to the memory module.

Further, according to the present invention, the memory module is a memory module composed of 2×y memory chips (an integer of y≧1) each having a storage capacity of x bits and having a data input/output of 4 bits; Preferably, the parity module is composed of y memory chips each having a storage capacity of x bits and having 1-bit data input/output.

[0008]

[Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In this embodiment, memory modules 1, 2, 3,
4, a parity module 5, a multiplexer 13,
14, decoder 15, OR gates 9, 10, 11,
It consists of 12.

Memory modules 1, 2, 3, 4 are 25
The parity module 5 is a module with a 32-bit data width consisting of eight 6K x 4-bit memory chips, and the parity module 5 is a module with a 4-bit data width consisting of four 1M x 1-bit memory chips. Multiplexer 13 outputs address signals MA2 to MA20 and SEL signal 8.
is input, and outputs memory address signals A0 to A8 to memory modules 1, 2, 3, 4 and parity module 5. The multiplexer 14 receives the address signal M
A21, MA22 and SEL signal 8 are input, and memory address signal A9 is output to parity module 5. The decoder 15 receives address signals MA21, MA22 as input, and receives memory enable signals 18, 19, 20, 2.
1 is output to OR gates 9, 10, 11, and 12. The RAS signal 16 is output to the OR gates 9, 10, 11, 12 and the parity module 5.
, 11, and 12 perform an OR operation on the RAS signal 16 and memory enable signals 18, 19, 20, and 21, and output the result to the memory modules 1, 2, 3, and 4. In addition, the memory control signal (CAS, WE) 17 is transmitted to the memory modules 1 and 2.
, 3, 4 and are output to the parity module 5.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2.
Explain using. FIG. 2 is a timing chart showing the operation of this embodiment.

When address signals MA21, MA22 and address signals MA2-MA20 are asserted, memory address signals A0-A8 are output from multiplexer 13 to memory modules 1, 2, 3, 4 and parity module 5, and the multiplexer 14 outputs a memory address signal A9 to the parity module 5. At the same time, one of the memory enable signals 18, 19, 20, and 21 becomes active by the decoder 15. Next, when the RAS signal 16 becomes active, the OR gates 9, 10, 11, and 12 OR the memory enable signals 18, 19, 20, and 21 with the RAS signal 16, and select one of the memory modules 1, 2, 3, and 4. Memory access is started for one module, and memory access is also started for the parity module at the same time. After a sufficient period of time has elapsed after RAS signal 16 becomes active, SEL signal 8
becomes active, the memory address signals A0 to A8 output from the multiplexer 13 are switched as shown by the arrow a in FIG. 2, and the memory address signal A9 output from the multiplexer 14 is switched as shown in the arrow b in FIG. It will be done. After the SEL signal 8 becomes active, when the memory control signal (CAS, WE) 17 becomes active, the address on the memory chip is determined. At this time, since the memory chip in the parity module 5 is divided into four by the memory address signal A9, one of the four areas corresponds to the memory modules 1, 2, 3, and 4 being accessed. be accessed.

As described above, in this embodiment, a memory circuit that performs a parity check can be constructed using one parity module for every four memory modules.

[0013]

As explained above, the present invention can reduce the number of memory chips by sharing one parity module among four memory modules in a memory circuit that performs a parity check. ,
This has the effect of making it possible to achieve miniaturization and space saving.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of this embodiment.

FIG. 3 is a block diagram showing a conventional memory control method.

[Explanation of symbols]

1, 2, 3, 4 Memory module 5 Parity module 6 32-bit memory data 7 4-bit parity data 8 Memory address switching signal (SEL) 9, 10
, 11, 12 OR gate 13, 14 Multiplexer 15 Decoder

Claims (3)

[Claims] Claim 1: A memory control method that performs a parity check, comprising: a memory module; and the memory module 4.
and one parity module for storing parity data of the four memory modules. 2. A multiplexer for switching between a row address and a column address excluding the upper 1 bit of the memory module and the parity module; and a multiplexer for switching between the row address and column address of the upper 16 bits of the parity module; 2. The memory control method according to claim 1, further comprising a decoder that generates an enable signal for switching access to the memory module. 3. The memory module is a 2×y memory chip having a storage capacity of x bits and having 4 bits of data input/output.
(an integer of y≧1), and the parity module is a parity module composed of y memory chips each having a storage capacity of x bits and having a data input/output of 1 bit. memory control method.