JPH0546467A - Dram controller and memory system using the same - Google Patents

Abstract

PURPOSE:To execute a nibble mode access in appearance against a dynamic random access memory(DRAM) supporting no nibble mode access. CONSTITUTION:A low address and a column address in an address signal from a host device are latched to latches 4 and 5 to be inputted in a multiplexer 6. The leset significant bit in the address signal and a mode signal representing an access mode are decoded after inputted to a decoder 7, and the multiplexer 6 is switched by a timing controller 8 based on the output of the decoder 7 to output a low address or a column address. By outputting a column address clock corresponding to a low address clock and each memory bank, it can be made access to each memory bank successively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM (Dynamic Random Access Memory) controller and an improvement in a memory system using the same.

[0002]

2. Description of the Related Art Conventional DRAMs such as "TC"
511001P "(1988 version" Toshiba MOS memory ")
Data Book (published by Toshiba Corporation), P189-211
Various access formats are supported,
Among them, the nibble mode is a convenient mode in which data of up to four consecutive addresses can be read and written at high speed.
Therefore, as a computer memory system, 1 to 4
If a word-accessible one is prepared, the processing speed of the computer can be improved.

By the way, a bit map display, which is often used as a display device of a computer, has an "TC524256P" as an image memory for storing the image information.
(See TOSHIBA MOS MEMORY data book 1988 edition (Toshiba Corp.), P668-700), etc., but they do not support nibble mode without exception.

Therefore, when a memory system including an ordinary DRAM and an image memory is required, conventionally, either one of the following two configurations is adopted.

1) The memory system supports only one word access.

2) 1-4 access to ordinary DRAM
Word access is allowed, but only one word is accessed for accessing the image memory.

[0007]

However, in 1), there is a problem that the processing speed of the entire memory system decreases. Further, in 2), the processing speed does not decrease much, but there is a problem that the load on the software increases because the access format is limited depending on whether the address is an image memory address or not.

As a DRAM control device for controlling these DRAMs, for example, "SN74ACT4503" (1
989 Edition "Memory Peripheral LSI" Data Book (Published by Texas Instruments Japan Ltd.), P61-78
Or "SN74ALS6301" (1989 version "Memory Peripheral LSI" data book (published by Texas Instruments Japan Ltd.), P101-120).
However, when these are used, the image memory itself does not support the nibble mode as described above, and therefore the image memory cannot be accessed in the nibble mode.

According to the present invention, a DRAM which does not support nibble mode access can perform memory access as if the nibble mode access was performed.
The present invention realizes an AM control device and a memory system using the same.

[0010]

In order to achieve the above object, the present invention provides claim 1 by specifying an address signal output from a host device and an access mode of 1 word access to 4 word access. A first latch for latching a row address in an address signal in a DRAM control device for accessing a plurality of memory banks composed of DRAMs based on a mode signal indicating whether
A second latch that latches the column address in the address signal, a multiplexer that outputs either the row address or the column address latched by the first and second latches, and a predetermined bit and the mode in the address signal. −
The decoder that decodes the read signal and generates a predetermined timing signal corresponding to each access mode, and switches the multiplexer based on the timing signal from the decoder, and switches the row address clock and the column address clock corresponding to each memory bank. 3. A DRAM controller including a timing controller for generating the signal, and a DRAM controller.
The timing controller controls the multiplexer based on the timing signal from the decoder, generates the row address clock and the column address clock corresponding to each memory bank, and controls a predetermined bit of the column address output from the multiplexer. A DRAM controller according to claim 1, and a DRAM controller according to claim 2 as claim 3, and an even address memory bank and an odd address memory bank composed of two DRAMs supporting a page mode. Propose a memory system.

[0011]

According to the first aspect of the present invention, the row address and the column address in the address signal are latched by the first and second latches, respectively. Further, a predetermined bit in the address signal and a mode signal are input to the decoder and decoded, and a predetermined timing signal corresponding to the access mode is output to the timing controller. Since the timing controller switches the multiplexer based on the predetermined timing signal, one of the row address and the column address in the address signal latched by the first and second latches is output to each memory bank, and
The timing controller outputs a row address clock and a column address clock corresponding to each memory bank, thereby accessing each memory bank.

Further, according to the second aspect, the timing controller controls a predetermined bit of the column address, which enables access in an access mode in which the number of words is larger than the number of memory banks.

According to a third aspect of the present invention, the address for the even address memory bank and the odd address memory bank can be switched by controlling a predetermined bit of the column address, thereby enabling 4-word access. ..

[0014]

1 shows the outline of a first embodiment of a memory system according to the present invention, in which 1 is a DRAM controller (hereinafter referred to as a memory controller) and 2 and 3 are DRs.
An image memory composed of AM. Memory controller 1
Is a 19-bit address signal AD and the address signal A
An address strobe signal AS indicating the timing when D is valid, a mode signal M1 indicating the type of memory access,
The M0 and the basic clock CK for creating the memory access timing are input from a host device (for example, CPU) (not shown) that performs memory access. The mode of memory access according to the mode signals M1 and M0 is, for example,
It is defined as in Table 1.

[0015]

[Table 1]

Further, from the memory controller 1, addresses MA8 to 0, which are multiplexed row and column addresses, are supplied to the image memories 2 and 3. Further, the image memories 2 and 3 have RAS0 and CA, respectively.
A pair of address latch clocks S0, RAS1, and CAS1 are supplied separately. At this time, the clock RA
The image memory 2 to which S0 and CAS0 are input constitutes an even address memory bank, and clocks RAS1 and CA
The image memory 3 to which S1 is input forms an odd address memory bank. The data bus to the image memories 2 and 3 is not shown because it is not directly related to the present invention.

FIG. 2 shows the details of the memory controller 1. In FIG. 2, 4 and 5 are 9-bit latches, and 6 is 9.
A bit multiplexer, 7 is a decoder, 8 is a timing controller, and 9 is an OR gate.

Of the 19-bit address signal AD described above, the upper 18 bits are latched by the latches 4 and 5 by 9 bits each, and are multiplexed via the multiplexer 6 to become the addresses MA8-0. Here, the address MA0 is ORed with the signal 10 from the timing controller 8 by the OR gate 9 so that it can be set to the high (H) level at an arbitrary timing. The least significant bit of the address signal AD and the mode signals M1 and M0 are input to the decoder 7 where they are decoded and their outputs are output to the timing controller 8.
Entered in. Based on the output 11 of the decoder 7 and the basic clock CK, the timing controller 8 generates clocks RAS1, RAS0, CAS1, CAS0, an address switching signal 12, and a signal 10 for setting the address MA0 to the H level.

Since a DRAM is used as the image memory, a refresh control circuit is actually required, but it is not shown because it is not directly related to the present invention.

Next, the operation of the above embodiment will be described with reference to the timing chart of FIG. 3, but here, the case of reading four words is shown.

In FIG. 3, the 19-bit address signal AD and the mode signals M1 and M0 are latched by the strobe signal AS at the timing before "1" of the clock CK, and their values are fixed (not shown). ), The values of the addresses MA8 to 0 are determined at the falling edge of the clock CK at "1", and the clocks RAS1 and RAS0 go to the low (L) level at the rising edge of the clock CK at "2". For example, RAD is taken into the image memories 2 and 3.

Next, when a column address, for example CAD, is output to the addresses MA8 to 0 at the falling edge of the clock CK at "2", only the clock CAS0 falls at the rising edge of the clock CK at "3" and an even address. The data (Data0) of the memory bank, that is, the image memory 2 is read to the data bus. Clock CAS0 is "4" of clock CK
When the clock CAS1 falls at the rising edge of the clock CK of "5", the odd address memory bank, that is, the data (Data
1) is read. Further, at the fall of "6" of the clock CK, the clock CAS1 becomes H level and at the same time the address MA0 becomes H level, and the next column address from the image memories 2 and 3, that is, the data of CAD + 1 (Dat
a2, Data3) are read every time the clocks CAS0, CAS1 fall.

Here, here, the clocks RAS1, RAS
The reason why the data can be read by changing the column address while 0 is at the L level is that the page mode of the image memory is used.

In this way, while keeping the clocks RAS1 and RAS0 at the L level, the clocks CAS0 and CAS1 are
Are alternately set to the L level, and the clock CAS1 is set first.
If the attention is paid to the least significant 2 bits of the original address signal AD by changing the address MA0 from the L level to the H level after the address becomes L level, the Dat at the address "00" is displayed.
a0, Data1 at address "01", Da at address "10"
This means that Data2 at the address ta2 and "11" is sequentially read. For this series of reading, "12" clocks are required for the clock CK.

On the other hand, in the case of reading only one word, only the clock RAS1 becomes L level when the odd address is accessed at the rising edge of the clock CK, and only the clock RAS0 becomes L level when the even address is accessed,
Only the clock CAS1 corresponding to the clock RAS1 or the clock CAS0 corresponding to the clock RAS0 becomes the L level at the rising of "3" of the clock CK,
Only one word can be read. In this case, to read one word, "6" clocks are required for the clock CK.

Therefore, in order to read 4-word data using 1-word access, "24" clocks are required for the clock CK, but if the 4-word access mode described above is used, half the "12" clocks are required. Data can be accessed at high speed. The same applies to the case of data writing. Further, in the 2-word access mode or the 3-word access mode, the operation is performed up to "7" clock or "9" clock of the clock CK, respectively.

Since the timing of the 4-word access mode in the first embodiment is the same as the nibble mode access of a normal DRAM, the nibble mode access can be made possible in the entire memory system, and the above-mentioned inconvenience occurs. do not do.

By the way, in the first embodiment, in order to achieve the nibble mode access, it suffices to prepare two image memories corresponding to the even address memory bank and the odd address memory bank. It had to be a DRAM that supported the mode.

FIG. 4 shows a second embodiment of the present invention in which the above-mentioned points are improved.
In the figure, 21 is a DRAM control device (memory controller), and 22, 23, 24 and 25 are image memories. The image memories 22, 23, 24 and 25 have the least significant 2 bits “00” and “0” of the address signal AD.
There are four memories corresponding to 1 ”,“ 10 ”, and“ 11 ”, respectively, and it is not necessary to support the page mode.

FIG. 5 is a timing chart of this embodiment. The difference from the first embodiment is the column address CAD.
No longer changes during the access, and the clock CASi (i = 0 to 3) is sequentially changed from the clock CAS0 to L.
That is, the level is reached and the data is read out as Data0 to Data3. In the case of 1-word access, only one set of clocks RASi and CASi is active, and memory access is performed.

[0031]

As described above, according to the first aspect of the present invention, the row address and the column address and the row address clock and the column address clock according to the access mode can be supplied to each memory bank. , DRAM that does not support nibble mode
Apparently, the plurality of memory banks can be accessed at the same timing as in the nibble mode, so that the data transfer rate can be improved and the performance of the computer system or the like can be improved.

Further, according to the second aspect of the present invention, the timing controller can control a predetermined bit of the column address, so that the access can be executed in the access mode in which the number of words is larger than the number of memory banks.

According to the third aspect of the present invention, the column address for the even address memory bank and the odd address memory bank can be switched, whereby the column address can be switched.
4 word access is possible and therefore 2 DRAs
A system capable of executing 4-word access can be realized by using M.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing details of a DRAM control device in FIG.

FIG. 3 is a timing chart of the device shown in FIGS. 1 and 2.

FIG. 4 is a configuration diagram showing a second embodiment of the present invention.

5 is a timing chart of the device shown in FIG.

[Explanation of symbols]

1, 21 ... Memory controller, 2, 3, 22, 23,
24, 25 ... Image memory, 4, 5 ... Latch, 6 ... Multiplexer, 7 ... Decoder, 8 ... Timing controller, 9 ... OR gate.

Claims (3)

[Claims] 1. A plurality of memory banks comprising DRAMs based on an address signal output from a higher-level device and a mode signal indicating which one of a 1-word access mode and a 4-word access mode is designated. In a DRAM control device for accessing a first address, a first latch for latching a row address in an address signal, a second latch for latching a column address in an address signal, and a first latch
And a multiplexer which outputs either the row address or the column address latched by the second latch, and a predetermined bit and a mode signal in the address signal are decoded to obtain a predetermined bit corresponding to each access mode. A DRAM control device comprising: a decoder for generating a timing signal; and a timing controller for switching a multiplexer based on the timing signal from the decoder and for generating a row address clock and a column address clock corresponding to each memory bank. .. 2. A timing for switching a multiplexer based on a timing signal from a decoder, generating a row address clock and a column address clock corresponding to each memory bank, and controlling a predetermined bit of a column address output from the multiplexer. The DRA according to claim 1, further comprising a controller.
M control device. 3. A memory system comprising: the DRAM control device according to claim 2; and an even address memory bank and an odd address memory bank formed of two DRAMs that support a page mode.