JPH056659A - Dynamic ram - Google Patents

Abstract

PURPOSE:To provide a device which increases frequency of access by a page mode of a DRAM for reduction of access time of the DRAM. CONSTITUTION:A plurality of row buffers 70-72 which retain data for one row (one page) are provided within a DRAM. Data is output from a row buffer which is specified by an WAY 103 in reading of a page-mode. Also, data is written to the row buffer which is specified by the WAY 103 in writing of the page mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM access time reduction device.

[0002]

2. Description of the Related Art In recent years, along with the increase in speed of microprocessors, the demand for higher speed of peripheral memories has increased. Therefore, a method of mounting a cache memory to shorten the access time of the entire memory is used.

On the other hand, the means for accelerating the DRAM itself which constitutes the main memory is a column access mode such as a high speed page mode, a static column mode or a nibble mode. There is a method to shorten the access time. Further, a method of increasing the speed by incorporating a cache memory in the DRAM is also used. A related device of this type is described in Japanese Patent Application Laid-Open No. 2-12687.

[0004]

The principle of shortening the access time by the column access mode described above is that when the same row address space (same page) is accessed in consecutive cycles, The second and subsequent accesses can omit the row address. But the program
It is composed of two types, a code part for executing instructions and a data part for storing variables and constants. In many cases, the processor fetches and accesses data alternately. For this reason, the rate of continuous accesses to the same page becomes low, and high-speed access using the column access mode cannot be sufficiently performed.

In the method of embedding the cache memory in the DRAM, it is difficult to increase the degree of integration because the extra memory cells are required for the cache memory, and the memory structure becomes complicated. There's a problem.

An object of the present invention is to realize a high speed access by a page mode even if the processor does not continuously access the same page by minimizing the change of the internal structure of the DRAM. Especially.

[0007]

In order to achieve the above object, the present invention has a plurality of buffers for one line designated by a row address, so that even if access to the same page is discontinuous, Enables high-speed access by the mode.

This is because, in a normal memory access, the data of the memory array is transferred to the designated buffer, and in the read in the page mode, the data is read from the designated buffer. The data is output, and the writing in the page mode is realized by writing the write data in the designated buffer.

[0009]

The DRAM of the present invention has a plurality of buffers each having a size corresponding to one row corresponding to a memory array of rows × columns. First, when the RAS signal is asserted by a read or write access, the row buffer designated by the external signal is written back to the memory array and then the data for one row indicated by the row address is deleted. Data from the memory array to the row buffer. When this access is a write, the bit designated by the column address is rewritten to write data. Next, when there is a read access by the page mode, the data is output from the designated column buffer. Also, in the light by page mode,
Only the bits specified by the column address in the column buffer are updated.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows the structure of a DRAM showing an embodiment of the present invention. Delayed lights are not supported for the sake of simplicity. In FIG. 1, the conventional DRAM
Signals RAS100, CAS101, DA which are also used
In addition to the TA 105, a signal WAY 103 for selecting a plurality of row buffers is added. The processing contents of the DRAM are roughly divided into four. The first processing is the writing back of data from the row buffer to the memory array, the second processing is the transfer from the memory array to the row buffer, and the third processing is the output of the data from the row buffer. The fourth processing is writing of write data to the row buffer.

First, when an access by non-page mode occurs, one of the data of the row buffers 70-72 is selected by the value of WAY 103 in the multiplexer 82 and stored in the memory array. To be done. One of the row buffers 30 to 32 is designated as the storage destination as a decoding result of the row decoder 41 after the selector 40 selects the WAY 103. That is, the row buffers 30 to 32 are for remembering the write-back destinations of the row buffers 70 to 72. The write timing to the memory array is performed at the falling edge of RAS100.

Next, a transfer is performed from the memory array 50 to the row buffers 70-72. First, at the fall timing of the RAS 100, the row address 110 is stored in the buffer of the way number designated by the WAY 103 of the row address buffers 30-32. Next, the stored row address is decoded and the data is read from the memory array. The read data is stored in any of the row buffers 70 to 72 having the way number designated by the WAY 103 through the selectors 60 to 62. At this time, if this access is a write, DATA105 is set to one bit designated by the column address in the selected row buffer.
Write data is written through selectors 60-62.

When this access is a read, a process of outputting the data of the row buffers 70 to 72 to the DATA 105 connected to the external bus is performed in addition to the above process. First, in the multiplexer 80, the WAY10
After selecting the line buffer with the way number specified in 3,
In the multiplexer 81, the data of the bit corresponding to the column address 111 is passed through the buffer 14 to DATA10.
Output to 5. Only this processing is performed in the read access by the page mode. This retrieves data from the row buffer without accessing the memory array,
High-speed access can be realized.

In the write access of page mode, D
The write data of the ATA 105 is transferred to the input buffer 13,
A process of rewriting one bit designated by the column address 111 of the row buffers 70 to 72 is performed through the selectors 60 to 62. In the selectors 60-62, WAY
Which of the plurality of row buffers is updated is selected by 103, and which bit is rewritten by the column address 111. Row buffers and other bits that are not selected are written back with the feedback of themselves. That is, the contents are saved. In this case as well, the row buffers 70 to 72 are accessed without accessing the memory array 50.
High-speed processing can be realized because it is simply rewritten.

Access in page mode is WAY
An arbitrary line buffer can be designated by the way number designated by 103. For example, if the way number "0" is used for instruction fetch and the way number "1" is used for data access, even if instruction fetch and data access occur alternately, a certain instruction fetch When the same page is accessed by the instruction fetch cycle generated after several cycles and the same cycle, the latter access can be performed at high speed by the page mode.

Table 1 shows the row buffers 70 to 7 shown in FIG.
The selection conditions in the selectors 60 to 62 for selecting the second input data are shown. Input data is D
It is selected from three types: ATA 105 write data, memory array 50 output data, and row buffer feed back. The write data is the column address 1 of the row buffers 70 to 72 selected by the WAY 103.
Only the bits specified by 10 are valid.

[0017]

[Table 1]

As for the data of the memory array 50, one of the row buffers 70 to 72 selected by the WAY 103 becomes effective in the case of the access by the non-page mode. For bits that do not correspond to either write data or memory array data, the feedback of the row buffer itself is valid. In this case, the contents of the line buffer are unchanged.

FIG. 2 is a timing chart showing a method of accessing the DRAM shown in FIG. The number of ways is set to 2 for the sake of explanation. The first access is a non-page mode read using the way number "1". At the same time as the ADDRESS 104 indicates the row address, the way number “1” is indicated by the WAY 103. At this time, in the DRAM, when the RAS 100 asserts, the contents of the row buffer with the way number "1" are written back to the memory array. Then, the contents of the memory array to be read are transferred to the row buffer with the way number "1".

The next access is a page mode read from the way number "0". Since this data already exists in the row buffer, the row with the way number "0" is accessed. Output data from the buffer.

Next, page mode to the way number "1"
This is a write access by the CAS1.
At the falling edge of 01, the bit corresponding to the column address in the row buffer with the way number "1" is rewritten into the write data.

The last access is a page mode read from the way number "0", which is the same as the second transfer and is read from the row buffer with the way number "0". -Output data.

[0023]

According to the present invention, by providing a plurality of row buffers, high-speed access by page mode can be realized even when access to the same page is discontinuous.

[Brief description of drawings]

FIG. 1 is a block diagram of a DRAM showing an embodiment of the present invention,

2 is a timing chart showing a method of accessing the DRAM of FIG.

[Explanation of symbols]

10 to 14 ... Input / output buffer, 30 to 32 ... Row address buffer, 40 ... Selector, 41 ... Row address decoder, 50 ... Memory array, 60-62 ...
Selector for row buffer, 70-72 ... Row buffer,
80-82 ... Multiplexer, 100 ... RAS signal,
101 ... CAS signal, 102 ... WE signal, 103 ...
WAY signal, 104 ... ADDRESS signal, 105 ...
DATA signal.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masataka Kobayashi             Stock, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Hitachi Microsoft Wear Systems Co., Ltd.             Within (72) Inventor Hideo Haruta             Stock, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Hitachi Microsoft Wear Systems Co., Ltd.             Within (72) Inventor Akira Ido             Stock, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Hitachi Microsoft Wear Systems Co., Ltd.             Within (72) Inventor Yasuhiro Furukawa             Stock, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Hitachi Microsoft Wear Systems Co., Ltd.             Within

Claims (6)

[Claims] 1. A dynamic RAM for time-divisionally specifying a row address and a column address, comprising a memory array specified by the row address and the column address, and a plurality of buffers for one row specified by the row address, Page
Access means using the row buffer according to a mode,
A dynamic RAM comprising means for selecting one from a plurality of row buffers according to an external signal. 2. A dynamic RA for outputting data from the row buffer selected by an external signal in the read access in the page mode according to claim 1.
M. 3. The dynamic RAM according to claim 1, wherein in the write access in the page mode, only the bit corresponding to the column address in the row buffer selected by an external signal is rewritten. 4. The normal read access other than the page mode according to claim 1, wherein a row buffer selected by an external signal is written back to the memory array and then a row address is used. A dynamic RAM for transferring data in the specified memory array to the row buffer and outputting the data from the row buffer. 5. A normal write access other than the page mode according to claim 1, wherein the row buffer selected by an external signal is written back to the memory array and then designated by the row address. A dynamic RAM for transferring the data of the memory array to the row buffer and writing the write data for the bit corresponding to the column address. 6. The row address strobe (RA) according to claim 1, wherein an external signal is provided as a selection means of a plurality of row buffers, and a decoding result of the external signal is used.
At the falling timing of S), the row buffer to which the data read from the memory array is transferred is selected, and the column
A dynamic RAM that selects a row buffer to be accessed by the page mode at the falling edge of the address strobe (CAS).