JPH05101650A - Refreshing method for dynamic memory - Google Patents

Abstract

PURPOSE:To comparatively increase the processing speed of an information processing equipment by omitting a useless refresh cycle from a DRAM. CONSTITUTION:When timing to move to the refresh cycle, that is, from a timing clock circuit 1 to an address counter 5, is indicated, an address to require refreshing is outputted from a refresh address decoder 7 to a flag check circuit 11. Simultaneously, the flag state of the same address indicated by a flag register 8 is decided by a flag check circuit 11, and an instruction to output a request signal is given to a request signal generator 12. Based on the instruction from a timing signal generating circuit 2, a refresh request signal is controlled by the request signal generator 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refresh system for a dynamic memory in a memory section of an information processing device.

[0002]

2. Description of the Related Art Conventionally, a refresh method of this type of dynamic memory (hereinafter referred to as DRAM) is incremented by one by an internal refresh address counter every refresh cycle and repeated for all row addresses of the memory. It was performing a refresh operation.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the AM refresh method, the refresh operation is performed at a constant cycle with respect to the row address of the entire memory space even though the data is newly held by reading or writing the memory data. Wasteful refresh cycle occurs, and CP
There is a problem in that the operation cycle of U cannot be effectively utilized and the processing speed of the information processing device is somewhat slowed.

[0004]

According to the refresh system of DRAM of the present invention, a flag register for temporarily storing the location of a row address accessed by a memory by a flag, and information of the flag from the flag register are received. A check circuit for checking the state of the flag and a generator for outputting the request signal when the refresh request generation condition is output by the check circuit and the refresh is necessary.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a refresh system of DRAM of the present invention.

In FIG. 1, a timing clock circuit 1
Measures the transition timing to the refresh cycle. The timing signal generation circuit 2 inputs a RAS (row address strobe) signal, a CAS (column address strobe) signal, an OE (output enable) signal, and a WE (write enable) signal, and various timing control signals inside the memory depending on its state. To occur. The address buffer 3 functions as a buffer for an address bus signal input from the outside. The row address decoder 4 decodes the row address input from the address buffer 3 and selects a memory cell. The address counter 5 counts refresh addresses. The address selector 6 selects a row address according to the operation mode. The refresh address decoder 7 decodes the refresh address output from the address counter 5. The flag register 8 has one flag for each row address and sets a flag for the accessed address. The memory cell 9 specifies a cell to be stored by a row address and a column address. The column address decoder 10 decodes the address input from the address buffer 3 and selects a memory cell. The flag check circuit 11 is a circuit for confirming the flag of the flag register 8. The request signal generator 12 outputs a REFREQ (refresh request) signal when refresh is necessary. Data input / output buffer 13
Inputs / outputs data between the memory cell 9 and the external interface.

Next, the operation of the refresh system of the DRAM of this embodiment will be described. When an address bus signal is externally input to the address buffer 3 for memory access and the RAS signal becomes active at the same time, the address is taken into the row address decoder 4. After that, the target memory area on the memory cell 9 is selected through the address selector 6, and at the same time, the flag on the flag register 8 for this address is set.

When the refresh operation is required, a clock is input from the timing clock circuit 1 to the address counter 5, the address output from the address counter 5 is decoded by the refresh address decoder 7 and input to the flag check circuit 11. Flag check circuit 1
1 fetches the flag of the register having the same address as the decoding condition indicated by the refresh address decoder 7 from the flag register 8 and checks whether the flag is set. If the flag is set, it means that the memory has been accessed, so the flag is reset without issuing a refresh request. If the flag is in the reset state, the request signal generator 12 outputs the REFREQ signal and shifts to the refresh cycle to set the flag of the flag register 8. The REFREQ signal releases the output when the refresh cycle is entered. After shifting to the refresh cycle, the address selector 6 is switched so that the refresh address from the address counter 5 becomes valid for the memory cell 9, and the target address is refreshed.

When the next refresh cycle is output, the same processing is performed, the refresh request is controlled according to the state of the flag to invert the flag, and if the refresh operation is required, the process is shifted to the refresh cycle.

[0010]

As is apparent from the above description, D of the present invention
According to the RAM refresh method, a wasteful refresh cycle is not generated, and the time for the cycle can be transferred to a cycle other than refresh.
The effect that the processing speed of the information processing device is relatively high is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a refresh system of a DRAM of the present invention.

[Description of Reference Signs] 1 timing clock circuit 2 timing signal generation circuit 3 address buffer 4 row address decoder 5 address counter 6 address selector 7 refresh address decoder 8 flag register 9 memory cell 10 column address decoder 11 flag check circuit 12 request signal generator 13 Data input / output buffer

Claims (1)

[Claims] 1. In a dynamic memory refresh system, a flag register for temporarily storing a location of a row address accessed by a memory by a flag,
A check circuit that receives the flag information from the flag register and confirms the state of this flag, and a generator that outputs a request signal when a refresh request generation condition is output by the determination of the check circuit and refresh is necessary A refresh method for a dynamic memory, characterized by being provided.