JPH0323587A - Parity generating and checking system for dram - Google Patents

Parity generating and checking system for dram

Info

Publication number
JPH0323587A
JPH0323587A JP1158000A JP15800089A JPH0323587A JP H0323587 A JPH0323587 A JP H0323587A JP 1158000 A JP1158000 A JP 1158000A JP 15800089 A JP15800089 A JP 15800089A JP H0323587 A JPH0323587 A JP H0323587A
Authority
JP
Japan
Prior art keywords
dram
parity bits
parity
time
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1158000A
Other languages
Japanese (ja)
Other versions
JPH0746495B2 (en
Inventor
Tsuyoshi Kumakura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PFU Ltd
Original Assignee
PFU Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PFU Ltd filed Critical PFU Ltd
Priority to JP1158000A priority Critical patent/JPH0746495B2/en
Publication of JPH0323587A publication Critical patent/JPH0323587A/en
Publication of JPH0746495B2 publication Critical patent/JPH0746495B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE: To increase the DRAM access speed by reading/writing only data at the time of access to a DRAM array from a CPU and generating and writing or checking parity bits at the time of refresh.
CONSTITUTION: The CPU or the like reads or writes only data from or in a DRAM array 1. When a DRAM write bit 4 is turned on at the time of refresh, parity bits are generated from data read out from the DRAM array 1 and are written in DRAM parity bits 3. When the DRAM write bit 4 is turned off then, a parity detecting circuit 5 performs the parity check based on data read out from the DRAM array 1 and parity bits read from DRAM parity bits 3. Consequently, it is unnecessary to provide a wait TW in consideration of generation and write of parity bits or delay due to parity check at the time of read/write access to the DRAM array 1. Thus, the DRAM access speed is increased.
COPYRIGHT: (C)1991,JPO&Japio
JP1158000A 1989-06-20 1989-06-20 DRAM parity generation / check method Expired - Lifetime JPH0746495B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1158000A JPH0746495B2 (en) 1989-06-20 1989-06-20 DRAM parity generation / check method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1158000A JPH0746495B2 (en) 1989-06-20 1989-06-20 DRAM parity generation / check method

Publications (2)

Publication Number Publication Date
JPH0323587A true JPH0323587A (en) 1991-01-31
JPH0746495B2 JPH0746495B2 (en) 1995-05-17

Family

ID=15662061

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1158000A Expired - Lifetime JPH0746495B2 (en) 1989-06-20 1989-06-20 DRAM parity generation / check method

Country Status (1)

Country Link
JP (1) JPH0746495B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6697992B2 (en) 2000-08-14 2004-02-24 Hitachi, Ltd. Data storing method of dynamic RAM and semiconductor memory device
JP2011186615A (en) * 2010-03-05 2011-09-22 Mitsubishi Electric Corp Device, method and program for checking error

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6697992B2 (en) 2000-08-14 2004-02-24 Hitachi, Ltd. Data storing method of dynamic RAM and semiconductor memory device
US7051260B2 (en) 2000-08-14 2006-05-23 Hitachi, Ltd. Data storing method of dynamic RAM and semiconductor memory device
US7318183B2 (en) 2000-08-14 2008-01-08 Elpida Memory, Inc. Data storing method of dynamic RAM and semiconductor memory device
JP2011186615A (en) * 2010-03-05 2011-09-22 Mitsubishi Electric Corp Device, method and program for checking error

Also Published As

Publication number Publication date
JPH0746495B2 (en) 1995-05-17

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