JPH0323587A - Parity generating and checking system for dram - Google Patents

Abstract

PURPOSE:To increase the DRAM access speed by reading/writing only data at the time of access to a DRAM array from a CPU and generating and writing or checking parity bits at the time of refresh. CONSTITUTION:The CPU or the like reads or writes only data from or in a DRAM array 1. When a DRAM write bit 4 is turned on at the time of refresh, parity bits are generated from data read out from the DRAM array 1 and are written in DRAM parity bits 3. When the DRAM write bit 4 is turned off then, a parity detecting circuit 5 performs the parity check based on data read out from the DRAM array 1 and parity bits read from DRAM parity bits 3. Consequently, it is unnecessary to provide a wait TW in consideration of generation and write of parity bits or delay due to parity check at the time of read/write access to the DRAM array 1. Thus, the DRAM access speed is increased.

Description

[Detailed Description of the Invention] [Required] Regarding the parity generation/checking method for checking the validity and parity of data written in DRAM, it is proposed that the CPU or the like write/read only the data when accessing the DRAM. , parity bisoto's life when refreshing
The purpose is to speed up memory access speed by performing write, read, and parity checks. It is equipped with a DRAM write-byft that is set on when data is written, and the CPU etc. write/write the DRAM array.
The above DR during read access and write access
If the AM write bit is turned on and the DRAM write bit is on at the time of refresh, a parity pit is created from the data read from the DRAM array and written to the DRAM parity pin. Pig DRA
If the M write bit is off, if it is off, the DRAM
A parity check is performed based on the data read from the array and the parity bit read from the DRAM parity bit. [Industrial Application Field] The present invention relates to a DRAM parity check method that checks the parity bits of data written in a DRAM and performs a parity check.

[Problems to be solved by conventional technology and invention] Conventionally, D
In order to improve the reliability of data in a storage device using a RAM or the like, as shown in FIG. 5, for example, a 1-bit parity bit is added to 8 bits of data and a set of 9 bits is written to the DRAM or the like. Then, at the time of reading, the parity of the 8-pin data is checked using this parity bit.

Therefore, when writing data to DRAM etc.
When reading data from a RAM, etc., the C
It is necessary to further provide a wait TW2 for memory access from the PU, which poses a problem in that the memory access speed decreases. In the present invention, the CPU or the like writes/reads only data when accessing DRAM, generates, writes, and reads parity bits during refresh, performs parity check on the read data and DRAM, and reads from memory access speed 3. The purpose is to speed up the parity degree based on the parity resolution. There is also a note on checking the status. [Means for solving the problem] The means for solving the problem will be explained with reference to Figure 1. In FIG. 1, a DRAM array 1 is a memory array using DRAMs to write data. The DRAM parity byft 3 is a memory configured using a DRAM in which parity data is written in association with the DRAM array 1. The DRAM write memory 4 is a memory configured using a DRAM that turns on when data is written to the DRAM array 1. Parity generator 2
For example, it generates parity data for data read from the DRAM array 1. The parity detection circuit 6 is connected to the DRAM array 1 [Operation] As shown in FIG.
Only data can be written to or read from the 7-rail. Also, when refreshing, DR
Regarding the data read from AM array 1, DRAM
When write bit 4 is on, the parity bit is read from the data read from DRAM array 1 and written to DRAM parity bit 3. On the other hand, when DRAM write bit 4 is off, the data read from DRAM array 1 and the DRAM parity bit are written to DRAM parity bit 3. The parity detection circuit 6 performs a parity check based on the parity focus read from the . Therefore, when the CPU or the like performs write/read access to the DRAM array 1, there is no need to provide a wait TW that takes into account the delay caused by parity bit generation, writing, or parity checking, and the DRAM array 1 can be accessed at high speed.
It becomes possible to access the M array. [Embodiment] Next, the structure and operation of an embodiment of the present invention will be explained in detail using FIGS. 1 to 4. In Figure 1,
The DRAM array 1 is a memory array in which, for example, 16 bits of DRAM (dynamic random access memory) are allocated to one address, which is inputted from the DRA arrays 1-1 and 1-2. For every 8 bits of these, 1 bit of DRAM parity bits 3-1 and 3-2 are added, and a total of 9 bits of 2All are used. The parity generator 2 includes parity generators 2-1 and 2.
-2, and performs parity focus on data read from DRAM arrays l-1 and 1-2, respectively. The DRAM parity bit 3 is composed of DRAM batch bits 3-1 and 3-2, and is a memory constructed using a DRAM in which one bit of parity data is written in association with the DRAM array 1. DRAM write bin 4 is a bi-soto memory constructed using a DRAM that turns on when data is written to the DRAM array. The write signal control circuit 5 receives this WE (write signal) and REFRESH (refresh signal) as inputs, and inputs the DRAM parity bits 3-1, 3-2, DRA
This is used to generate write signals to M write bit 4, etc. The parity detection circuit 6 includes a parity generator 2-1,
The parity bit from DRAM array 2-2 and the parity bit read from DRAM parity bits 3-1 and 3-2 are input, and the parity check of the data read from DRAM array 11 and 1-2 is performed. ．． Next, using the flowchart in Figure 2, we will explain in detail the operation of the composition command in Figure 1. +II CPU etc. are connected to DRAM array 1-1. ．． Operation when accessing 12: 010... sets line access to on at W/R and W. This means that when the CPU or the like performs write access (W) to DRAM array l, data is input to DRAM arrays t-t, l-2 via the input data bus and *RAS, *CAS, *WE are input! Pig DRAM
While supplying and writing to array 1-LL-2, DRA
Set M write bit 4 on to indicate that data has been written. Also, when the CPU etc. makes read access, *RAS, *CAS, WF! ．． is supplied to the DRAM arrays 1-1 and 1-2, and the data is sent out from the output data path. Therefore, CPtJ etc. are connected to DRAM arrays 1-1 and 1-2.
There is no need to monitor and write the parity bit or read and check the parity bit as in the past when writing/reading the DRAM, and there is no need to provide a wait cycle TW in DRAM access in consideration of delays caused by these. Figure 3: No need to provide TW2
), it becomes possible to access DRAM arrays 1-1 and 1-2 at high speed. (2) Operation in the case of parity bit generation/writing and parity check during refresh: (2) determines whether DRAM write bit 4 is on or not. If YES (if parity has not been written), [
Write the parity bit in [phase] and [phase]. NO
(If parity has been written), [Phase], ■
Check the parity with ↑. It will be explained below. Opa, *RAS, *CAS) f-DRAM array l-L
The parity bits manually read out in 1-2 by the parity generators 2-1 and 2-2 are input to the parity detection circuit 6, and the DR
Input the parity bit read from the AM parity bit 3-123-2 to the parity bint detection circuit 6,
Compare the two and perform a parity check. Regarding the result of this parity check, if it is OK with O, execute the steps after ■ for the next address in [Phase], and on the other hand, if it is NO with ■
If so, it is considered a parity error. [Phase] is the parity generated by the parity generators 2-1 and 2-2 for the data read out by inputting *RASS*CAS, WE to the DRAM array L-L 1-2, parity bit 3-
Write in 1, 3-2. At this time, the parity bit detection circuit 6 is masked to prevent a parity error from occurring, and the DRAM write bit 4 is reset to off (a message indicating that the parity bit has been written is displayed).
). Therefore, during refresh, when it is determined that parity has not been written by referring to DRAM write bit 4, the DRAM
By writing the corrected parity bits to parity bins 3-1 and 3-2, and on the other hand, checking the parity of DRAM array 1-L 1-2 when it is determined that parity has already been written, the CPU etc. It becomes possible to read, write, and check parity bits without delaying cycles that access -1 and 1-2. FIG. 3 shows a waveform diagram during reading according to the present invention.

This is a waveform diagram when the CPU or the like performs read access to the DRAM arrays 11 to 12, and as indicated by diagonal lines in the figure, data can be read out with only one wait cycle TWI. In the past, data was read out during wait cycle TW2, as shown in the shaded area in FIG. Here, in Fig. 3, SYSCLOCK is the system clock, CI'tlCLOCK is the clock that the CPU operates, TW is the wait cycle, 8LE is the address delay signal, *RD is the read signal, and *IIEADY is the ready signal (this signal 9, the wait cycle TWI is inserted), the address/data is DRAM array 1-1,
! -2 represents the address/data to be input. Figure 4 shows
A parity generation/check waveform diagram during refresh of the present invention is shown. This means that DRAM array 1 is
- Write the parity bits generated from the data read from DRAM arrays 1-1 and 1-2 to DRAM parity bits 3-1 and 3-2, or write the parity bits generated from the data read from DRAM arrays 1-1 and 1-2. A waveform diagram is shown when inputting the data to the parity detection circuit 6 and manually inputting the parity focus read from the DRAM parity bits 3-1 and 3-2 to the parity detection circuit 6, and performing parity check by comparing the two. In addition, in the figure, RDXX is read data, I? PL [lT
, IIPUDT is DRAM parity bit 3-L
Parity bit read from 3-2, WPLDT,
Is WPUDT a DI? AM Paritibisoto 3-1, 3-
Parity bint for writing to 2, jl[lTB is D
Represents the bit to write to RAM write bit 4 (
(See Figure 1). [Effects of the Invention] As explained above, according to the present invention, the CPU etc.
r? Writes/reads only data when accessing AM array 1, and performs parity bit generation/writing/parity check during refresh and refresh.
Because it uses the same technology, the CPU, etc. are connected to the DRAM array.
There is no need to provide a weight TW that takes into account the delay due to parity generation/checking when accessing the DRAM array, and the DRAM array can be accessed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of one embodiment of the present invention, FIG. 2 is a flowchart explaining the operation of the present invention, FIG. 3 is a waveform diagram when reading according to the present invention, and FIG. FIG. 5 shows an example of a conventional circuit, and FIG. 6 shows a waveform diagram of the conventional circuit. In the figure, 1, l-L L-2 is DRAM array 2, 2-1
, 2-2 is a baritin generator, 3, 3-1 3-2
represents the DRAM parity bit, 4 represents the DRAM write bit, and 6 represents the parity detection circuit.

Claims (1)

[Claims] A parity generation/check method for generating a parity bit of data written to a DRAM and performing a parity check, comprising: a DRAM array (1) to which data is written;
A DRAM parity bit (3) in which parity data is written in association with the M array (1), and a DRAM write bit (4) which is set on when data is written to the DRAM array (1). The CPU and the like write/read access to the DRAM array (1), and the DRAM array (1) is accessed during write access.
If the write bit (4) is set on and the above DRAM write bit (4) is on during refresh, the DR
Generate a parity bit from the data read from the AM array (1), write it to the DRAM parity bit (3), and turn off the DRAM write bit (4),
On the other hand, when the DRAM is off, a parity check is performed based on the data read from the DRAM array (1) and the parity bit read from the DRAM parity bit (3). Parity generation/check method.