JPH0323587A - Parity generating and checking system for dram - Google Patents

Abstract

PURPOSE: To increase the DRAM access speed by reading/writing only data at the time of access to a DRAM array from a CPU and generating and writing or checking parity bits at the time of refresh.

CONSTITUTION: The CPU or the like reads or writes only data from or in a DRAM array 1. When a DRAM write bit 4 is turned on at the time of refresh, parity bits are generated from data read out from the DRAM array 1 and are written in DRAM parity bits 3. When the DRAM write bit 4 is turned off then, a parity detecting circuit 5 performs the parity check based on data read out from the DRAM array 1 and parity bits read from DRAM parity bits 3. Consequently, it is unnecessary to provide a wait TW in consideration of generation and write of parity bits or delay due to parity check at the time of read/write access to the DRAM array 1. Thus, the DRAM access speed is increased.

COPYRIGHT: (C)1991,JPO&Japio