JP2568443B2 - Data sizing circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data sizing circuit in a data flow type system in which data flows in synchronization with a pulse and processing is performed in accordance with the movement of the data.

[Prior Art] FIG. 13 shows a conventional example of a data sizing circuit (data read / write circuit) in a data flow type system.

In the figure, 203 and 204 are pipeline registers, and 205 is a memory body (storage element).

A packet input line 212 is connected to the pipeline register 203. Here, a parallel bit string that includes information such as data required for memory access, an address signal, and a read / write flag for designating read / write and propagates in synchronization with a pulse is referred to as a packet.

The write data output from the pipeline register 203 is supplied to the memory main unit 205 via the write data line 221, and the read / write flag output from the pipeline register 203 is output via the read / write flag line 222 to the memory main unit 2.
05, and the address signal output from the pipeline register 203 is supplied to the memory main unit 205 via an address line 223.
Supplied to

A part of the packet output from the pipeline register 203 and whose contents are not changed by the memory access is supplied to the pipeline register 204 via the packet transfer line 224.

The read / write data from the memory main body 205 is supplied to the pipeline register 204 via the read data line 225. The packet output line 214 is connected to the pipeline register 204.

Reference numerals 201 and 202 denote transfer control circuits for controlling the propagation of pulses. The transfer control circuit 201 is connected to a pulse input line 211. When a pulse is supplied to the transfer control circuit 201, a write pulse is immediately supplied to the pipeline register 203, and a pulse is supplied to the transfer control circuit 202 after a predetermined time delay. When a pulse is supplied to the transfer control circuit 202, a write pulse is immediately supplied to the pipeline register 204, and a pulse is output to the pulse output line 213 after a certain time delay.

When a write pulse is supplied, the pipeline registers 203 and 204 capture and hold data on an input line and output the data at the same time.

The memory body 205 is configured to operate as follows.

When the read / write flag from the read / write flag line 222 is set to the read value, a read operation is performed in the memory main body 205, and the data at the address specified by the address signal from the address line 223 is read.
Output to 5.

When the read / write flag from the read / write flag line 222 is set to a write value, a write operation is performed in the memory main body 205, and the write data from the write data line 221 is transferred to the address specified by the address signal from the address line 223. Is written. At the same time, the value of the write data line 221 is output to the read data line 225 as it is.

The operation when reading from the memory body 205 in the above configuration will be described.

A packet whose read / write flag is set to a read value is supplied to the packet input line 212, and a pulse is supplied to the pulse input line 211. As a result, a write pulse is supplied from the transfer control circuit 201 to the pipeline register 203, and a packet supplied from the packet input line 212 is captured and held in the pipeline register 203. Then, after a predetermined time, a pulse is supplied from the transfer control circuit 201 to the transfer control circuit 202.

During this time, the read / write flag from the read / write flag line 222, the address signal from the address line 223, and the write data from the write data line 221 are stabilized to the contents of the packet, the read operation is performed in the memory 205, and the read to the read data line 225 is performed. The output data is output.

When a pulse is supplied from the transfer control circuit 201 to the transfer control circuit 202, the transfer control circuit 202 sends the pipeline register 2
04 is supplied with a write pulse, and the pipeline register 204 receives and holds data supplied from the read data line 225 and the packet transfer line 224,
Output to the packet output line 214. Then, after a predetermined time, a pulse is output from the transfer control circuit 202 to the pulse output line 213.

 In this way, a series of read processing is performed.

Regarding the operation when writing to the memory main body 205, by setting the write value to the read / write flag of the packet supplied to the packet input line 212, the write process is performed in the same manner as the above-described series of read process. Be executed.

[Problems to be Solved by the Invention] However, the data sizing circuit of FIG. 13 has disadvantages as described below.

For the sake of explanation, it is assumed that the system has a data width of 32 bits, that is, each of the write data line 221 and the read data line 225 has a width of 32 bits.

First, all reading and writing of the system is performed in a batch of 32 bits.

In this system, for example, even if it is desired to handle 8-bit width data, if the data is read out, the other 24-bit contents are destroyed at the same time as the writing of the 8-bit width data.

When handling 8-bit data, only the lower 8 bits of 32 bits are treated as valid, that is, the processing can be used as 32 bits and the valid as 8 bits. It is wasted and the memory utilization efficiency is reduced.

Second, the unit of the system address is automatically 32 bits.

Assume that the unit of the address is 8 bits.
Even if the data width itself is 32 bits, if the address is, for example, address 1 (in units of 8 bits), the arrangement is 32 bits.
Since the data spans two words of the bit width and two addresses need to be accessed, the example shown in FIG. 13 cannot be handled.

Excluding such unhandled processing, the data width is fixed at 32 bits in this system.

If it is recognized that only the lower 8 bits of the 8-bit data are treated as valid, the upper surplus bits are wasted.

 The unit of the address is 32 bits.

If it is desired to use 8 bits as a unit, the data is arranged in multiples of four.

It becomes extremely restrictive.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data sizing circuit that can read and write a plurality of types of data having different data widths at arbitrary addresses without wasting memory.

Means for Solving the Problems According to the present invention, an address unit is N bits, a data line width is M × N bits (M and N are positive integers), and data flows in synchronization with a pulse. In a data sizing circuit of a data flow type system in which processing is performed in accordance with movement of M, an M-bit N-bit storage element having an arbitrary depth and which can be accessed at any time, and a maximum of M × N bits are stored in the M storage elements. A write circuit for writing data, a read circuit for reading data of a maximum of M × N bits from M storage elements, and a given address in accessing the M storage elements by the write circuit and the read circuit And a circuit for detecting whether or not to access each of the M storage elements based on
The writing circuit includes: a first rotation circuit that rotates input data in a predetermined direction in N-bit units based on a given address; and a rotation circuit that stores the rotated data in M storage elements.
A circuit for providing a given address and an address obtained by adding M to the given address;
A circuit for reading M × N-bit-width data from a given address and an address obtained by adding M to the given address of each of the memory elements; A circuit for synthesizing the N-bit width data, and a second rotation for rotating the synthesized M × N-bit width data in N-bit units in a direction opposite to that of the first rotation circuit based on the given address. And a circuit for reading and writing M types of data from an N-bit width to an M × N-bit width at an arbitrary address.

[Operation] In the above configuration, in a data flow type system in which the address space is in N-bit units and the data line width is M × N-bit, M types of data from N-bit width to M × N-bit width can be arbitrarily transferred. Read and write to addresses. Therefore, it is possible to eliminate restrictions on use such that the data width must be in M × N bits and the address must be in M × N bits.

Embodiment An embodiment of the present invention will be described below with reference to FIG. In this example, the data line width is 32 bits, the address unit is 8 bits (bytes), and the data types handled are 8-bit data (byte data), 16-bit data (word), and 32-bit data. (Long word).

In FIG. 1, 111 to 114 are pipeline registers,
121 is an input swapper, 122 is an incrementer, 123 is an access detector, 124 is a memory body (storage element), 125 is a selector, 126 is an output swapper, and 127 is a T flip-flop.

Reference numeral 101 denotes a copy control circuit that controls pulse propagation and duplication, 102 denotes a branch control circuit that controls pulse propagation and distribution, and 103 denotes a transfer control circuit that controls pulse propagation.

A pulse input line 131 is connected to the copy control circuit 101.
When a pulse is supplied to the duplication control circuit 101, a write pulse is immediately supplied to the pipeline register 111, and after a predetermined time delay, the branch control circuit 102
Pulses are supplied continuously. The interval between the two pulses is set longer than the above-described delay time.

When a pulse is supplied to the branch control circuit 102, a write pulse is immediately supplied to the pipeline register 112. Then, depending on whether the pulse is an odd-numbered pulse or an even-numbered pulse, a pulse is supplied to the corresponding next stage after a delay of a predetermined time. That is, when the number is an odd number, a pulse is supplied to the pipeline register 113, and when the number is an even number, a pulse is supplied to the transfer control circuit 103.

When a pulse is supplied to the transfer control circuit 103, a write pulse is immediately supplied to the pipeline register 114, and a pulse is output to the pulse output line 133 after a delay of a predetermined time.

When a write pulse is supplied, the pipeline registers 111 to 114 capture and hold data on the input line,
Output at the same time.

A packet input line 132 is connected to the pipeline register 111. The read / write flag output from the pipeline register 111 is supplied to the memory main body 124 via the read / write flag line 144.

The write data output from the pipeline register 111 is supplied to an input stage 32-bit rotator (input swapper) 121 via an input data line 141. The lower two bits of the address signal output from the pipeline register 111 are supplied to the input swapper 121 via a lower address line 142 as a control signal.

In the input swapper 121, the 32-bit width input data on the input data line 141 is rotated in 8-bit units according to the value of the lower 2 bits of the address signal supplied on the lower address line 142. In this case, as shown in FIG. 2, the values of the lower two bits of the address signal are "0", "1", "2".
And "3", the rotation is controlled to the left by 0, 8, 16 and 24 bits, respectively. In FIG. 2, D1 to D4 are 8-bit data that constitute 32-bit write data.

The write data whose rotation is controlled by the input swapper 121 is supplied to the memory main body 124 via the write data line 143.

The above bits other than the lower two bits of the address signal output from the pipeline register 111 are
The signal is supplied to an address adder (incrementer) 122 via.

In the incrementer 122, “4” is added to the address value of one of the two duplicated packets. In this example, “4” is added to the later packet in the time series among the two packets.

In this case, the same pulse as the pulse supplied from the copy control circuit 101 to the branch control circuit 102 is output from the T flip-flop 127.
The output signal of the T flip-flop 127 is supplied to the incrementer 122 via the packet identification line 148 as a packet identification flag. In the incrementer 122, the packet identification flag identifies whether the packet is before or after the packet, and performs the above-described processing.

Here, a parallel bit string that includes information such as data required for memory access, an address signal, a read / write flag, a flag indicating a data type, and propagates in synchronization with a pulse is referred to as a packet. Also, of the two packets, the one whose address value is not processed is the first packet, and the address value is “4”.
Is referred to as a second packet.

The upper address output from the incrementer 122 is
The data is supplied to the memory main body 124 via the upper address line 149.

The lower two bits of the address signal output from the pipeline register 111 and the flag indicating the data type are supplied to the access detector 123 via the access code 149, and the access detector 123 has the T flip-flop 1
27, a packet identification flag is supplied via a packet identification line 148.

In this access detector 123, the lower 2
According to the value of the bit, the flag indicating the data type, and the value of the packet identification flag, the memory body 124 is assigned to each of 8 bits in the 32-bit width input data on the write data line 143
Is detected. Each access signal is supplied to the memory main body 124 via four chip enable lines 150.

Details of the access detector 123 will be described with reference to FIG.

FIG. 3 shows an example in which data of three types is arranged in a memory space having a width of 32 bits.

Here, four cells arranged side by side with a width of 8 bits constitute a 32-bit wide long word that can be read and written simultaneously by one memory access, and the 0th byte and the 0th byte from the lower (right) direction. They are called 1 byte, 2nd byte and 3rd byte. Each long word is arranged in the depth direction of the memory (downward in the figure) according to the upper address excluding the lower 2 bits.

Data A is byte data and the address is 0, data B is a word and address is 6, data C is a word and address is 15, data D is a long word and address is 25, and data E is a long word. There are 36 addresses.

Here, an operation of the access detector 123 regarding the data C will be described as an example.

The value of the address excluding the lower 2 bits of the first packet (when it is set to 0) is 12, and that of the second packet is
It is 16 due to the function of the incrementer 122.

For the first packet, the access detector 123 detects that only the third byte is permitted to access. Then, for the second packet, it is detected that only the 0th byte is permitted to access. Which byte from the 0th byte to the 3rd byte is permitted is uniquely determined by the data type and the value of the lower 2 bits of the address signal. Also, the first
The packet and the second packet are identified based on the value of the packet identification flag.

A part of the packet output from the pipeline register 111 and whose contents are not changed by the memory access is supplied to the pipeline register 112 via the packet transfer line 157.

Read data from the memory main body 124 is supplied to the pipeline register 112 via the read data line 145.

The memory body 124 is configured as a 32-bit wide memory in which four 1-byte wide memories are arranged in the horizontal direction. The position in the depth direction in the memory space is indicated by the upper address line.
It is specified by the value of the upper bits excluding the lower two bits supplied at 149, and whether or not each byte in the horizontal direction can be accessed is specified by the access signals supplied by the four chip enable lines 150.

Accordingly, when the read / write flag supplied on the read / write flag line 144 is set to write for the byte requested to be accessed, the corresponding byte data on the write data line 143 is written, while the read / write flag is set. When set to read, the read data line
The byte data is read to the corresponding position on 145.

Note that a function of outputting initial value data to a corresponding position on the read data line 145 may be provided for a byte for which access is not permitted by the chip enable line 150 at the time of reading.

Data output from the pipeline register 112 is supplied to the pipeline register 113 and the selector 125 via the data line 151. The packet portion other than the data output from the pipeline register 112 is the packet transfer line 15
8 to the pipeline register 113. Then, the data output from the pipeline register 113 is supplied to the selector 125 via the data line 152,
The lower two bits of the address signal output from the pipeline register 113 are supplied to the lower
It is supplied as a control signal via 4.

The selector 125 is for synthesizing one valid longword from the longword of the first packet output from the pipeline register 113 and the longword of the second packet output from the pipeline register 112.

Here, the operation will be described using data C in FIG. 3 as an example.

The longword of the first packet contains the value of the longword at address 12, and the longword of the second packet contains the value of the longword at address 16. At this time, the selector 125 selects the long word of the first packet as the third byte, selects the long word of the second packet as the 0th byte to the second byte, and synthesizes one longword. . This selection is uniquely determined by the value of the lower two bits of the address signal supplied on the lower address line 154.

At this time, there may be a function for initializing the value of each bit of the first and second bytes, which are meaningless areas. Which byte to initialize is uniquely determined by the lower two bits of the address signal and the data type.

The long word synthesized by the selector 125 is the data line 153
Is supplied to a 32-bit data rotator (output swapper) 126 for the output stage. The lower two bits of the address signal output from the pipeline register 113 are supplied to the output swapper 126 via a lower address line 155 as a control signal.

In the output swapper 126, the 32-bit width input data on the data line 153 is rotated in 8-bit units according to the value of the lower 2 bits of the address signal. In this case, when the values of the lower two bits of the address signal are “0”, “1”, “2”, and “3”, 0 bit, 8 bits,
Only 16 bits and 24 bits are controlled to rotate right.
This is the reverse operation of the input swapper 121 described above.

After the rotation, the first byte to third byte, the second byte to
A function for initializing the value of each byte of the third byte may be provided.

The data whose rotation is controlled by the output swapper 126 is supplied to the pipeline register 114 via the output data line 156. The portion of the packet excluding the data output from the pipeline register 113 is supplied to the pipeline register 114 via the packet transfer line 159. A packet output line 134 is connected to the pipeline register 114.

Next, the operation of the system will be described. As an example,
Although described using data C in FIG. 3, similar operations are performed for byte data, words, and long words at other arbitrary positions.

 First, an operation related to writing will be described.

A packet whose write value is set in the read / write flag, word value is set in the flag indicating the data type, and the packet in which the address value of the address signal is set to 15 is a packet input line.
Supplied to 132.

3 as the field for data on the packet input line 132
Two bits are prepared, and it is essentially arbitrary to assign the bit field to the 16-bit data C. However, in this system, it is assumed that the data C is located in the area of the lower 2 bytes.

When a pulse is supplied to the pulse input line 131 (shown in FIG. 5A), a write pulse is supplied from the duplication control circuit 101 to the pipeline register 111 (FIG. 5B).
), The pipeline register 111 holds the contents of the packet supplied from the packet input line 132,
The contents are output.

FIG. 4A shows the pipeline register 111 at this point.
Shows part of the output. Here, C0 and C1 are a lower byte and an upper byte in the data C, respectively.

At this point, the packet identification flag output from the T flip-flop 127 indicates the first packet (the fifth packet).
The output of the pipeline register 111 is the first
Treated as a packet.

Therefore, in the incrementer 122, the upper address (shown in FIG. 5E) supplied from the pipeline register 111 via the address line 147 is not processed, and the value of the upper address 12 via the upper address line 149 is not processed. Is the memory body 1
24 (shown in FIG. 5F).

In the input swapper 121, the 32-bit input data on the input data line 141
The write data is rotated to the left by a bit, and the rotation-controlled write data is supplied to the memory body 124 via the write data line 143.

Further, writing is instructed to the memory main body 124 by the read / write flag supplied from the read / write flag line 144. The access signal formed by the access detector 123 based on the lower 2 bits of the address signal supplied from the access code 146 and the flag indicating the data type, and the packet identification flag supplied from the packet identification line 148 is output to the chip enable line. The data is supplied to the memory main body 124 via 150, and access to only the third byte is permitted.

As a result, the write operation is performed in the memory main body 124, and only the third byte in the long word at the address 12 is written.
The C0 data is written (see the portion surrounded by the thick line of the first packet in FIG. 4B).

After a delay of a predetermined time, the first pulse is supplied from the copy control circuit 101 to the branch control circuit 102 (fifth pulse).
A write pulse is supplied from the branch control circuit 102 to the pipeline register 112 (shown in FIG. 5G), and the pipeline register 112 holds the content of the first packet, Is output (fifth
FIG. K).

At the same time, the T flip 127 is triggered by the first pulse output from the duplication control circuit 101, the value of the packet identification flag indicates the second packet (shown in FIG. 5D), and the pipeline register 111 Is treated as a second packet.

Therefore, in the increment 122, “4” is added to the upper address (shown in FIG. 5E) supplied via the upper address line 147, and the value 16 of the upper address is added via the upper address line 149 to the memory main body 124. (Shown in FIG. 5F). Then, the access detector 123 permits access to only the 0th byte.

As a result, the write operation is performed again in the memory 124, and only the 0th byte in the long word at the address 16 is written.
The C1 data is written (see the portion surrounded by the thick line of the second packet in FIG. 4B).

At this point, the contents of the first packet appear as its output and the contents of the second packet appear as its input in the pipeline register 112. FIG. 4C shows a part of the first packet and the second packet.

Further, after a delay of a fixed time from the point of supply of the first write pulse to the pipeline register 112, a write pulse is supplied from the branch control circuit 102 to the pipeline register 113 (shown in FIG. 5H). Then, the contents of the first packet are held in the pipeline register 113, and the contents are output (shown in FIG. 5L).

After that, the duplication control circuit 101 sends the branch control circuit 102 the second
The first pulse is supplied (shown in FIG. 5C), a write pulse is supplied from the branch control circuit 102 to the pipeline register 112 (shown in FIG. 5G), and the pipeline register 112 The contents of two packets are retained,
The contents are output (shown in FIG. 5K).

At the same time, the T flip-flop 127 is triggered by the second pulse output from the duplication control circuit 101, and the value of the packet identification flag returns to a state indicating the first packet (shown in FIG. 5D).

At this point, the output of pipeline register 113 is the first
Because of the contents of the packet (shown in FIG. 5L), the value of the long word in the first packet is output on the data line 152. Since the output of the pipeline register 112 is the content of the second packet (shown in FIG. 5K), the value of the long word in the second packet is output on the data line 151.

Here, in the selector 125, based on the value 3 of the lower 2 bits of the address signal supplied from the lower address line 154,
The 0th to 2nd bytes are selected from the long data in the second packet, and the 3rd byte is selected from the long data in the first packet, and one longword is generated. FIG. 4D shows a long word generated at this time.

Further, in the output swapper 126, the data on the data line 153 is rotated rightward by 24 bits based on the value 3 of the lower 2 bits of the address signal supplied from the lower address line 155, Is output. FIG. 4E shows the data on the output data line 156.

Then, after a delay of a certain time from the point of supply of the second write pulse to the pipeline register 112, a pulse is supplied from the branch control circuit 102 to the transfer control circuit 103 (shown in FIG. 5I), and this transfer is performed. A write pulse is supplied from the control circuit 103 to the pipeline register 114 (shown in FIG. 5J). The pipeline register 114 holds the long word on the output data line 156 and a part of the contents of the first packet which is the output of the pipeline register 113, and simultaneously outputs the packet to the packet output line 134 (the 5 shown in FIG. M). Further, after a delay of a certain time, a pulse is output from the transfer control circuit 103 to the pulse output line 133, and a series of write operations is completed.

Next, an operation related to reading will be described. A case where the word at address 15 and the data C are read out will be described as an example in the same manner as the above-described write-related operation.

A packet in which the read value is set in the read / write flag, the word value is set in the data type flag, and the packet in which the address value of the address signal is set to 15 is the packet input line.
Supplied to 132.

Then, when a pulse is supplied to the pulse input line 131,
The same operation as in the above-described writing is performed. First, the contents of the first packet are supplied to the memory main body 124 through the signal lines 144, 143, 149, and 150.

At this point, the read / write flag from the read / write flag line 141 is read, the value of the upper address from the upper address line is 12, and the access signal from the chip enable line 150 permits only the third byte. From the main body 124, the long word at address 12 including the C0 data is read and output on the read data line 145.
Then, the first packet including the read long word is sent to the pipeline register 1 via the pipeline register 112.
Transferred to 13.

Further, the same operation as at the time of writing is performed, and the contents of the second packet are supplied to the memory main body 124 through the signal lines 144, 143, 149, and 150. The data is read out and output on the read data line 145. Then, the content of the second packet including the read rung word is held in the pipeline register 112.

At this point, the contents of the first packet are held in the pipeline register 113 and the contents of the second packet are held in the pipeline register 112 (see FIG. 4C).

Thereafter, the same operation as in the writing is performed, an output packet (shown in FIG. 4E) is output to the packet output line 134, and a series of reading operations is completed.

Thus, according to the present example, the 8-bit width, the 16-bit width,
Four types of data having a 24-bit width and a 32-bit width can be read / written at an arbitrary address, so that restrictions on use can be largely eliminated.

In the example of FIG. 1, the access detector 123
At the time of reading, as in the case of writing, access to any of the 0th byte to the 3rd byte is permitted according to the lower 2 bits of the address signal, the flag indicating the data type, and the value of the packet identification flag. However, at the time of reading, access may be permitted to all bytes from the 0th byte to the 3rd byte irrespective of the lower 2 bits of the address signal, the flag indicating the data type, and the value of the packet identification flag. This is because, in the case of reading, even if an unnecessary byte is accessed, only an empty reading is performed, and no inconvenience occurs as an operation of the system.

As described above, in order to change the operation of the access detector 123 between writing and reading, for example, as shown in FIG. 6, a read / write flag from the read / write flag line 144 is supplied to the access detector 123 as a control signal. It should be done.

Also, in the example of FIG. 1, the output swapper 126 is arranged at the subsequent stage of the selector 125. However, as shown in FIG. 7, the output swapper 126 is provided by combining the selector 125 with the function of the output swapper 126. It may be omitted.

In this case, the selector 125 is configured to operate as follows.

That is, the selector 125 is supplied with a total of 64 bits of a long word in the 32-bit width first packet and a long word in the 32-bit width second packet as the data input.

The 0th to 3rd bytes of the long word in the first packet are respectively located at the 0th to 3rd bytes, and the 0th to 3rd bytes of the longword in the second packet are respectively assigned to the 0th to 3rd bytes. It is arranged at the position of 4 bytes to 7 bytes.

Then, in accordance with the values “0”, “1”, “2”, and “3” of the lower 2 bits of the address signal from the lower address line 154, the 0th byte to the 3rd byte, the 1st byte to the 4th byte, respectively. , Second byte to fifth byte, third byte to sixth byte
The value of the byte is selected and output to the output data line 156.

Since the third byte of the long word in the second packet is not selected, the selector 125 starts from the beginning.
May not be supplied.

By the way, regarding the data A, B, E, etc. in FIG.
Essentially no access of the second packet is required.

However, according to the configuration of FIG.
Output two mechanically continuous pulses, which are supplied to the branch control circuit 102.
A packet memory access cycle is also inserted.

FIG. 8 shows an example in which such unnecessary memory access cycles are not inserted.

In this example, as described above, the access detector 123 determines whether the memory main body 124 can be accessed according to the lower two bits of the address signal supplied by the access code 146 and the value of the flag indicating the data type. In addition to generating the signal, a second access signal indicating whether or not the access of the second packet is necessary is generated. The necessity of accessing the second packet depends on the lower two bits of the address signal.
It is uniquely determined by the flag indicating the bit and the data type. The second output from the access detector 123
The access signal is supplied as a control signal to the copy control circuit 101 and the branch control circuit 102 via the control line 160.

The duplication control circuit 101 determines that the value of the second access signal
It is configured to perform the following operations.

That is, when access to the second packet is necessary, when a pulse is supplied from the pulse input line 131, a write pulse is immediately supplied to the pipeline register 111, and after a certain time delay, the branch control circuit 102 And two pulses are continuously supplied to the T flip-flop 127. This is the same operation as the duplication control circuit 101 in the example of FIG.

Next, when access to the second packet is unnecessary, when a pulse is supplied from the pulse input line 131, a write pulse is immediately supplied to the pipeline register 111, and after a certain time delay, the branch control circuit Only one pulse is supplied to 102.

The branch control circuit 102 also determines the value of the second access signal as 2
It is configured to perform the following operations.

That is, when access to the second packet is required, when a pulse is supplied from the duplication control circuit 101, a write pulse is immediately supplied to the pipeline register 112. When the pulse is an odd-numbered pulse, the pulse is supplied to the pipeline register 113 after a delay of a predetermined time, while when the pulse is an even-numbered pulse, the pulse is supplied to the transfer control circuit 103 after a delay of a predetermined time. Supply. This is the same operation as the branch control circuit 102 shown in FIG.

Next, when access to the second packet is unnecessary, when a pulse is supplied from the duplication control circuit 101, a write pulse is immediately supplied to the pipeline register 112, and the pipeline register 112 captures input data. , And after a time necessary for outputting, a pulse is supplied to the pipeline register 113. Further, after a delay of a predetermined time, a pulse is supplied to the transfer control circuit 103.

In the above configuration, for example, for the data C in FIG. 3, the access of the second packet is necessary,
The same operation as in the example of the figure is performed.

For example, data A, B, E, etc. in FIG.
No packet access is required. Therefore, when a pulse is supplied from the pulse input line 131, only one pulse is supplied from the copy control circuit 101 to the branch control circuit 102, and therefore, only one memory access cycle occurs.

FIGS. 9A to 9M show time charts of the example of FIG. 8 when the access of the second packet is unnecessary. The data A (address 0) in FIG. 3 is used as an example.

Thus, by configuring as shown in FIG. 8,
Since unnecessary memory access cycles are not inserted, the copy control circuit 101 can quickly return to the standby state for the input of the next packet, and processes more packets in the unit time than in the example of FIG. be able to.

By the way, when the order of the packets passing through the memory body 124 is considered in chronological order, in the example of FIG. 1, “4” is added to the upper address first for the first packet whose upper address is not processed. The second packet that has flowed later.

FIG. 10 shows another embodiment of the present invention.
In this example, the second packet is configured to flow first. In FIG. 10, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this example, the initial value of the packet identification flag is the second
The state indicates a packet. Also, the incrementer 12
In 2, “4” is added to the upper address of the previous packet in the time series, and the upper address of the subsequent packet is not processed.

Reference numeral 104 denotes an erase control circuit for controlling the erasure and propagation of the pulse. The erase control circuit 104 is supplied with a pulse from the copy control circuit 101. When a pulse is supplied to the erase control circuit 104, a write pulse is immediately supplied to the pipeline register 112. When the write pulse is an even number, a pulse is supplied to the transfer control circuit 103 after a delay of a certain time. That is,
The odd-numbered pulses are erased after being supplied to the pipeline register 112.

Read data from the memory main body 124 is supplied to a first data input unit of the pipeline register 112 via a read data line 145. The long word output from the first data output unit of the pipeline register 112 is supplied to the selector 125 via the data line 152 and is also supplied to the second data input unit of the pipeline register 112. And this pipeline register 112
The long word output from the second data output unit is supplied to the selector 125 via the data line 151.

 Other configurations are the same as those in the example of FIG.

Next, the operation of the system will be described. As in the case of the example shown in FIG. 1, a description will be given using data C in FIG. 3, but the same operation is performed for byte data, words, and long words at other arbitrary positions.

 First, an operation related to writing will be described.

A packet whose write value is set in the read / write flag, word value is set in the flag indicating the data type, and the packet in which the address value of the address signal is set to 15 is a packet input line.
Supplied to 132. A 32-bit data field is provided for the packet input line 132, and is essentially
The bit field to which the data C having the 16-bit width is allocated is arbitrary, but in the present system, it is assumed that the data C is located in the area of the lower 2 bytes.

When a pulse is supplied to the pulse input line 131 (shown in FIG. 11A), a write pulse is supplied from the replication control circuit 101 to the pipeline register 111 (FIG. 11B).
), The pipeline register 111 holds the contents of the packet supplied from the packet input line 132,
The contents are output.

FIG. 4A shows the pipeline register 111 at this point.
Shows part of the output. Here, C0 and C1 are a lower byte and an upper byte in the data C, respectively.

At this point, the packet identification flag output from the T flip-flop 127 indicates the second packet (the eleventh packet).
The output of the pipeline register 111 is the second
Treated as a packet.

Therefore, in the incrementer 122, “4” is added to the upper address (shown in FIG. 11E) supplied from the pipeline register 111 via the upper address line 147,
The upper address value 16 is supplied to the memory body 124 via the upper address line 149 (shown in FIG. 11F).

In the input swapper 121, the 32-bit input data on the input data line 141
The write data is rotated to the left by a bit, and the rotation-controlled write data is supplied to the memory body 124 via the write data line 143.

Further, writing is instructed to the memory main body 124 by the read / write flag supplied from the read / write flag line 144. A flag indicating the lower two bits of the address signal supplied from the access code 146 and a data type;
An access signal generated by the access detector 123 based on the packet identification flag supplied from the packet identification line 148 is supplied to the memory main body 124 via the chip enable line 150, and access to only the 0th byte is permitted.

As a result, the write operation is performed in the memory main body 124, and only the 0th byte in the long word at the address 16 is written.
The C1 data is written (see the portion surrounded by the thick line of the second packet in FIG. 4B).

Then, after a delay of a certain time, the first pulse is supplied from the copy control circuit 101 to the erase control circuit 104 (the eleventh pulse).
A write pulse is supplied from the erase control circuit 104 to the pipeline register 112 (shown in FIG. C).
(Shown in Figure G). So this pipeline register
The value of the long word in the second packet is output to the first data output unit 112 (shown in FIG. 11J).

At the same time, the T flip-flop 127 is triggered by the first pulse output from the duplication control circuit 101, the value of the packet identification flag indicates the first packet (shown in FIG. 11D), and the pipeline register The output of 111 is treated as the first packet.

Therefore, in the incrementer 122, the upper address line 1
Upper address supplied via 47 (shown in FIG. 11E)
Is not processed, and the upper address value 12 is supplied to the memory body 124 via the upper address line 149 (shown in FIG. 11F). Then, the access detector 123 permits access to only the third byte.

As a result, the write operation is performed again in the memory main body 124, and the C0 data is written into only the third byte in the long word at the address 12 (see the portion surrounded by the thick line of the first packet in FIG. 4B).

At this point, the contents of the second packet appear as an output and the contents of the first packet appear as an input in the pipeline register 112. FIG. 4C shows a part of the first packet and the second packet.

Thereafter, the copy control circuit 101 sends the second
The first pulse is supplied (shown in FIG. 11C), and the erase control circuit 104 supplies a write pulse to the pipeline register 112 (shown in FIG. 11G). Therefore, the value of the long data in the first packet is output to the first data output unit of the pipeline register 112 (shown in FIG. 11J), and the value of the long data in the second packet is output to the second data output unit. The value of the word is output (shown in FIG. 11K).

At the same time, the T flip 127 is triggered by the second pulse output from the duplication control circuit 101, and the value of the packet identification flag returns to the state indicating the second packet (No.
11 shown in Figure D).

At this point, the output of the first data output of pipeline register 112 is the value of the long word in the first packet (shown in FIG. Word value is output. The output of the second data output unit of the pipeline register 112 is the content of the long word in the second packet (FIG. 11K).
, The value of the long word in the second packet is output on the data line 151.

Here, in the selector 125, based on the value 3 of the lower 2 bits of the address signal supplied from the lower address line 154,
The 0th to 2nd bytes are selected from the long data in the second packet, and the 3rd byte is selected from the long data in the first packet, and one longword is generated. FIG. 4D shows a long word generated at this time.

Further, in the output swapper 126, the data on the data line 153 is rotated rightward by 24 bits based on the value 3 of the lower 2 bits of the address signal supplied from the lower address line 155, Is output. FIG. 4E shows the data on the output data line 156.

Then, after a delay of a fixed time from the point in time when the second write pulse is supplied to the pipeline register 112, a pulse is supplied from the erase control circuit 104 to the transfer control circuit 103 (first pulse).
A write pulse is supplied from the transfer control circuit 103 to the pipeline register 114 (shown in FIG. 11I). The pipeline register 114 holds a long word on the output data line 156 and a part of the content of the first packet which is the output of the pipeline register 112, and simultaneously outputs the packet to the packet output line 134 (the 11 shown in Figure L). Further, after a delay of a certain time, a pulse is output from the transfer control circuit 103 to the pulse output line 133, and a series of write operations is completed.

Next, an operation related to reading will be described. An example in which the data C of the word at address 15 is read in the same manner as the above-described operation related to writing will be described.

A packet in which the read value is set in the read / write flag, the word value is set in the data type flag, and the packet in which the address value of the address signal is set to 15 is the packet input line.
Supplied to 132.

Then, when a pulse is supplied to the pulse input line 131,
The same operation as in the above-described writing is performed. First, the contents of the second packet are supplied to the memory main body 124 through the signal lines 144, 143, 149, and 150.

At this point, the read / write flag from the read / write flag line 144 is read, the value of the upper address from the upper address line 149 is 16, and the access signal from the chip enable line 150 permits only the 0th byte. The long word at address 16 including the C1 data is read from the memory body 124 and output on the read data line 145. Then, the second packet including the read long word is held in the pipeline register 112.

Further, the same operation as at the time of writing is performed, and the contents of the first packet are supplied to the memory main body 124 through the signal lines 144, 143, 149, and 150. The memory main body 124 performs a read operation, and the long word at the address 12 including the C0 data is read. The data is read out and output on the read data line 145. Then, the content of the first packet including the read long word is held in the pipeline register 112.

At this time, the long word in the first packet is output to the first data output unit of the pipeline register 112, and the long word in the second packet is output to the second data output unit ( (Illustrated in FIG. 4C).

Thereafter, the same operation as in writing is performed, an output packet (shown in FIG. 4E) is output to the packet output line 134, and a series of reading operations is completed.

Thus, according to the present example, the 8-bit width, the 16-bit width,
Four types of data having a 24-bit width and a 32-bit width can be read / written at an arbitrary address, and the same operation and effect as in the example of FIG. 1 can be obtained. There is an advantage that one can be reduced.

In the example of FIG. 10, as in the example of FIG.
It goes without saying that modifications can be made as shown in FIGS.

In the example shown in FIG. 10, a write pulse is supplied from the duplication control circuit 101 to the pipeline register 111, the data output from the pipeline register 111 passes through the input swapper 121, and the upper address of the address signal is incremented. Go through 122 and memory body 1
After the access is completed by 24 and the read data of the read data line 145 is determined, it is necessary to supply a pulse from the copy control circuit 101 to the erase control circuit 104. After the second pulse is supplied from the duplication control circuit 101 to the erase control circuit 104, it is necessary to input a pulse accompanying the next read / write packet from the pulse input line 131. That is, when viewed from the input-side peripheral device, it is necessary that the time sending interval of the packet requesting the memory access be a certain value or more.

FIG. 12 shows another embodiment of the present invention, in which the time transmission interval of packets can be shortened. 12, parts corresponding to those in FIG. 10 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this example, a pipeline register 115 is inserted after the input swapper 121 and the incrementer 122, and a pipeline register 116 is inserted after the selector 125.
Is inserted.

Further, a transfer control circuit 105 for controlling the propagation of the pulse is provided at a stage subsequent to the copy control circuit 101. When a pulse is supplied from the replication control circuit 101 to the transfer control circuit 105, a write pulse is immediately supplied to the pipeline register 115, and a pulse is supplied to the erasure control circuit 104 after a certain time delay.

Further, a transfer control circuit 106 for controlling the propagation of the pulse is provided at a stage subsequent to the erase control circuit 104. When a pulse is supplied from the erase control circuit 104 to the transfer control circuit 106, a write pulse is immediately supplied to the pipeline register 116, and a pulse is supplied to the transfer control circuit 103 after a certain time delay.

When the write pulse is supplied, the pipeline registers 115 and 116 take in and hold the data on the input lines, and output the data at the same time.

In this example, the input swapper 121 and the incrementer 1
Outputs such as 22 are temporarily stored in the pipeline register 115 and then supplied to the memory body 124, and the selector 125
Is temporarily stored in the pipeline register 116 and then supplied to the output swapper 126. The other operations related to the memory access are exactly the same as those in the example of FIG. 10, and the description is omitted.

Thus, according to this example, for example, the input swapper 12
1, the output of the incrementer 122 etc. is a pipeline register
Since the output of the pipeline register 111 is stabilized and the outputs of the input swapper 121 and the incrementer 122 are stabilized after being held once at 115 and then supplied to the memory main body 124, the access of the memory main body 124 is terminated. Without waiting,
A pulse can be supplied from the copy control circuit 101 to the transfer control circuit 105. Therefore, according to this example, it is possible to reduce the time sending interval of the packet requesting the memory access, and it is possible to improve the throughput of the system.

Here, the example in FIG. 12 corresponds to the example in FIG. 10, but the example corresponding to the example in FIG. 1 can be similarly configured.

In the above embodiment, the data line width is 32 bits,
Although an example of a system having an address unit of 8 bits and three types of data types of 8 bits, 16 bits and 32 bits is shown, the present invention is not limited to this. For example, the data line width is 16 bits, the address unit is 8 bits, the data type is 8 bit width and 2 types of 16 bits width, the data line width is 16 bits, the address unit is 4 bits, and the data type is 4 bits width and 8 bits width Various systems such as three types of bit width, data line width of 64 bits, address unit of 8 bits, and data types of four types of 8-bit width, 16-bit width, 32-bit width, and 64-bit width should be similarly configured. Can be.

[Effects of the Invention] As described above, according to the present invention, up to M types of data whose data type is from N bits to M × N bits (M and N are positive integers) are arranged at arbitrary addresses. be able to. Therefore, it is possible to largely eliminate restrictions on use such that the data type must be in the unit of M × N bits and the address must be in the unit of M × N bits. As a result, the use efficiency of the memory can be improved by coexisting data of a plurality of data types having different data widths and densely arranging the address space using a data type having a small width, and improving the use efficiency of the memory in the address space. It is possible to realize simplicity of use by arbitrarily arranging data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 to 5 are diagrams for explaining the embodiment, FIGS. 6 to 8 are block diagrams of a modification of the example of FIG. FIG. 9 is a diagram for explaining the operation of the example in FIG.
FIGS. 10 and 12 are configuration diagrams showing another embodiment of the present invention, FIG. 11 is an operation explanatory diagram of the example of FIG. 10, and FIG. 13 is a configuration diagram of a conventional example. 101: Copy control circuit 102: Branch control circuit 103, 105, 106 Transfer control circuit 104: Erase control circuit 111 to 116 Pipeline register 121: Input swapper 122: Incrementer 123: Access detector 124 ... Memory body 125 ... Selector 126 ... Output swapper 127 ... T flip-flop

Claims (1)

(57) [Claims] An address unit is N bits, a data line width is M × N bits (M and N are positive integers), data flows in synchronization with a pulse, and processing is performed as the data moves. A data sizing circuit of a data flow type system, comprising: M N-bit-width storage elements having an arbitrary depth and accessible at any time; and a writing circuit for writing data of a maximum of M × N bits into the M storage elements. A read circuit for reading data of a maximum of M × N bits from the M storage elements, and an access to the M storage elements by the write circuit and the read circuit, based on a given address. A circuit for detecting whether or not to access each of the M storage elements, wherein the write circuit converts input data in a predetermined direction in N-bit units based on a given address. Times A first rotation circuit for performing the read operation, and a circuit for applying the rotated data to the given address of the M storage elements and an address obtained by adding M to the given address. From the given address of the M storage elements and the address obtained by adding M to the given address, the circuit calculates M × M
A circuit for reading the N-bit width data, a circuit for synthesizing one M × N-bit width data from the two read data, and combining the synthesized M × N-bit width data with the given address And a second rotation circuit for rotating the first rotation circuit in a reverse direction in units of N bits based on the first rotation circuit. A data sizing circuit characterized by being able to read and write data.