JP2741514B2 - Multi CPU system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a multi-CPU system that transfers initial program data from one CPU to another CPU. (Prior Art) Generally, when configuring a system with multiple CPUs, each CPU always requires a system program memory. Therefore, in the case of a multi-CPU, software management of the system program becomes very complicated and complicated. As one of the countermeasures, a method of collecting the system program in one memory and transferring the program to a memory of a system having no program at the time of initializing has been widely used. FIG. 2 is a block diagram showing the basic configuration of a conventional multi-CPU system. This means that the first CPU 1.1 and the second CPU 2
・ It is a multi-CPU system that transfers programs to the system of 7. The ROM 2 (first memory) and RAM 3 belong to the CPU 1.1, and the RAM 4 and RAM 5 (second memory) belong to the CPU 2.7. Reference numeral 9 denotes data from the CPU 1.1 port and the address bus 11
▲ (write) signal 9a,
Buffer enable signal (G) 9b, reset signal (RESE)
T) a decoder that outputs 9e, 10 is an 8-bit data bus, 11 is an 8-bit address bus, 6 is a buffer that controls the bus state by a buffer enable signal 9b from the decoder 9, and 12 is a buffer. Is a D-type flip-flop, which latches data with a signal from the CPU 1.1. By the way, the RAM 5 is a RAM in order to enable writing at the time of initializing, and it can be said that the RAM 5 is actually a ROM in which programs of the CPUs 2 and 7 are stored. ROM2 stores programs for CPU1.1 and CPU2.7. At the time of initialization, CPU 1.1
7 is read and stored in a register, the address data of the RAM 5 to which the program is to be transferred is output to the D-type flip-flop 12, and latched by the signal ▲ ▼. Further, the CPU 1.1 stores the data corresponding to the address in the register and outputs the data to the D-type flip-flop 12, and also latches the data by the signal ▲. As a result, the data to be transferred and its address are set in the D-type flip-flop 12. When the CPUs 2.7 have a 16-bit address bus and a data bus, similar operations are required by separating each operation into upper data and lower data. In FIG. 2, CPUs 2 and 7 have 16 bits of address and 8 data.
Takes a bit example. After data is set in the D-type flip-flop 12, the buffer 6 is enabled by the buffer enable signal 9b decoded by the decoder 9 by the address output from the CPU 1.1 and the reset. Then, the data latched by the flip-flop 12 is output onto the data bus 10 of the CPUs 2.7 and ▲.
The write signal 9a as a signal is decoded by the decoder 9, so that writing to the RAM 5, that is, transfer of a program becomes possible. During the transfer of the program, the CPUs 2 and 7 are of course reset. After the transfer of all the programs, the reset is released, and the operations of the CPUs 1, 1 and 2 are performed. (Problems to be solved by the invention) However, considering the recent increase in the amount of software, CPU2
-Repeating the procedure of setting 8-bit data three times for all of the seven programs and writing the data to the RAM 5 results in a large time loss. Also, providing the D-type flip-flop 12 and the bus buffer 6 for each bus increases the amount of hardware, and since the actual use time is the initial time, data exchange between CPUs is mainly performed. In this case, further simplification can be considered. Such a conventional multi-CPU system can be said to be a very inefficient system in consideration of the program transfer time. As a method having excellent program transfer efficiency, there is a DMA (direct memory method). However, since this requires a DMA controller, there is a disadvantage that the system configuration becomes complicated. The present invention has been made in view of the above circumstances, and is a multi-function capable of shortening the time required for transferring a program from one CPU to the other CPU at the time of initial processing with a simple hardware configuration. The purpose is to provide a CPU system. (Means for Solving the Problems) The present invention provides, as means for solving the above-mentioned problems, first and second programs capable of executing respective program contents independently of each other.
It has a second CPU, and the first CPU on the first CPU
Multi-C which transfers the program data of the second CPU stored in the memory of the second CPU to the second memory of the second CPU
In the PU system, a decoder that outputs a decode signal based on a control signal output from the first CPU and a decoder provided on an address bus between the first CPU and the second CPU and transmitted from the decoder. A bus buffer that allows only the read address signal of the program data output from the first CPU to pass from the first CPU to the second CPU at the time of initialization by a decode signal as a gate signal that comes in And a decoder signal provided on a data bus between the first CPU and the second CPU and transmitted from the decoder as a gate signal. To the first CP
A bus transceiver that allows the passage of only the program data signal read by U, and the decoder reads the program data stored in the first memory when the first CPU reads the program data stored in the first memory. Outputting a decode signal as the gate signal to the bus buffer and the bus transceiver, and outputting a decode signal as a write signal to the second memory. I do. (Operation) In the above configuration, the first CPU, upon initializing,
The program data on the second CPU side and its address stored in the first memory are read, and at the same time, the decoder outputs a decode signal as a gate signal to the bus buffer and the bus transceiver. The state at this point can be said to be a state in which preparation for data transfer from the first memory to the second memory is completed. Then, when the decoder outputs a decode signal as a write signal to the second memory, the program data transmitted through the data bus is transmitted to the address of the second memory specified by the signal from the address. Written. In this case, it is considered that the operations from the time when the first CPU reads the first memory to the time when the second memory is written are performed at substantially the same timing. May be. Therefore, the second from the first CPU side
In this case, the total transfer time when data is transferred to the CPU side can be greatly reduced. (Embodiment) FIG. 1 is a block diagram showing a circuit configuration of a system according to an embodiment of the present invention. In all the drawings, the same reference numerals indicate the same or corresponding parts. In FIG. 1, a bus buffer IC6 (three-state buffer) is provided on an address bus 11, and a bus transceiver 8 (a bidirectional bus buffer with a built-in D flip-flop) is provided on a data bus 10. . Then, the CPU 1.1 reads the program to be transferred from the ROM 2 and outputs the control signals 1a, 1b and 1c to the decoder 9 at the same time as the decoder 9, and the decoder 9 outputs the decode signals 9a to 9e based on the input of these control signals. As shown, the data is output to the bus buffer IC 6, the bus transceiver 8, the RAM 5, and the CPUs 2.7. With such a configuration, the program contents can be written to the RAM 5 simultaneously with the reading of the program contents of the ROM 2 by the CPUs 1.1. That is, the decoder 9 outputs the control signal 1 from the CPU 1.1.
a, 1b, 1c and a signal from the address bus 11, and a buffer enable signal for the address bus 11, that is, a bus buffer.
Enable signal (G) 9b of IC6, buffer enable / latch signal (G) 9c of bus transceiver (HC652) controlling data bus 10, and reset (RESE) of CPUs 2.7
T) Decode the signal 9a, the write (▲ ▼) signal 9d to the RAM 5 of the CPU 2.7, and the upper address signal 9a of the RAM 5 of the CPU 2.7. At the time of initialization, the CPU 1.1 resets the CPU 2.7, and enables the bus buffer 6 in the direction A → B, that is, in the direction from the CPU 1.1 side to the CPU 2.7 side.
The program to be transferred is read (empty read). At this time, the lower address of the data currently read by the CPU 1.1 is also output to the address bus 11 of the CPU 2.7 via the bus buffer 6. Then, at the time of transferring the program, the upper address 9a is output from the decoder 9 to the CPUs 2 and 7, and the address synthesized therewith becomes the real address for the RAM 5. Further, the bus transceiver 8
Are buffer enabled in the A → B direction, and a buffer enable / latch signal 9c (G) is supplied from the decoder 9, so that the data is also output to the data bus 10 on the CPU 2.7 side. Here, CPU 1.1 outputs ▲ ▼ signal 9d to RAM5.
If a signal is output and decoded, the data read by the CPU 1.1 is written to the address to which the RAM 5 is to be written. By repeating this procedure, the data read by the CPU 1, that is, the program, is successively written to the decoded address. After the transfer of the program, the bus buffer 6 of the address bus 11 is no longer enabled, and the bus transceiver 8 can be used as a bus register (bidirectional D-type flip-flop). CPU
In other words, the operations of CPU 1.1 and CPU 2 and 7, respectively,
It is possible to exchange data between them. In the above configuration, the address data is divided into an upper address and a lower address, and a decode signal is used for the upper address. Therefore, the number of address buses 11 can be reduced as compared with the conventional case. In other words, the program data to be transferred is usually stored in a specific memory area in ROM 2, but if this memory area is specified by a decode signal indicating the upper address, the lower address signal May be transferred to the RAM 5 through the address bus 11. A bus buffer IC 6 and a bus transceiver 8 which can be enabled by a decode signal
Since the CPU 1 and 1 read data from the ROM 2 at the same time, they are enabled by the decode signal from the decoder 9, and the RAM 5 has the address bus 11.
And data from the data bus 10 are written. Therefore, the transfer time can be significantly reduced. For example, in the conventional case (see FIG. 2), first, CPU1
The data corresponding to the upper and lower addresses of the RAM 5 is read from M2, stored in its own register, and then latched by the D flip-flop 12 with the signal. In addition, CP
U1 · 1 stores the data corresponding to the address in the register, and causes the D flip-flop 12 to latch the lower address (1 byte) and the data (1 byte) corresponding to the upper address of the RAM 5 respectively. With the address (2 bytes) and data (1 byte) all latched, the bus buffer 6 is enabled by the control signal of the CPU 1.1 and the enable signal 9b decoded by the address, and the 3-byte data is converted to the CP.
It is output to each bus on the U2.7 side. The output of the ▲ ▼ signal 9a decoded by the control signal and the address of the CPU 1.1 causes the preceding data to be written to the RAM5. Here, the data of the D flip-flop 12 is set three times (for three bytes), and one write to the RAM 5 is performed at another timing, and the transfer of the one-byte data is completed. On the other hand, according to the present invention (see FIG. 1), the CPU 1
When 1 outputs an address and reads the contents of RAM 5 contained in ROM2, the above address is set to a lower address (1 byte) by the control signal of CPU1.1 and the control signal 9b decoded by the above address, and the CPU2 bus And at the same time, the upper address 9a is output to the upper address bus on the CPU 2.7 side. Similarly, as a result of outputting the gate latch signal 9c to the bus transceiver 8, the data (1 byte) output first from the ROM 2 is latched. This data is output to the data bus on the CPU 2.7 side because the bus transceiver 8 is set to output in the A → B direction. Then, it is written into the RAM 5 by the control signal of the CPU 1.1 and the signal 9d decoded by the address. As a result, in the present invention, the transfer of 1-byte data to the RAM 5 is completed at substantially the same timing by one data read by the CPU 1.1, so that the transfer of 1-byte data is about 3 Completed in one-second time. Even if two-byte data is transferred according to the present invention, it can be reduced to about one half as compared with the conventional one-byte data transfer. [Effects of the Invention] As described above, according to the present invention, a bus buffer and a bus transceiver are provided on an address and a data bus, and these are controlled by a gate signal from a decoder. Since the configuration is such that the program data is written to the second memory by the write signal from the decoder at substantially the same timing as the reading to the first memory, the hardware configuration is simple. In addition, it is possible to greatly reduce the time required for transferring a program from one CPU to the other CPU.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing a circuit configuration of a conventional example. 1 CPU 1 (first CPU), 2 ROM (first memory), 5 RAM (second memory), 6 bus buffer IC, 7 CPU 2 (second CPU) , 8... Bus transceiver, 9... Decoder, 10... Data bus, 11.

Claims (1)

(57) [Claims] It has first and second CPUs that can execute respective program contents independently of each other, and the first CPU
In a multi-CPU system for transferring program data of the second CPU stored in the first memory of the second CPU to the second memory of the second CPU, a control signal output from the first CPU And a decoder that outputs a decode signal based on the first and second CPUs. The decoder is provided on an address bus between the first CPU and the second CPU. A bus buffer that allows only the read address signal of the program data output from the first CPU to pass from the CPU side to the second CPU side, and data between the first CPU and the second CPU. The program which is provided on the bus and is read by the first CPU from the first CPU to the second CPU at the time of initializing by a decode signal as a gate signal sent from the decoder. A bus transceiver that allows the passage of only the program data signal, the decoder comprising: when the first CPU reads program data stored in the first memory at an initial time, the bus buffer and the bus buffer; A multi-CPU system, comprising: outputting a decode signal as the gate signal to a bus transceiver; and outputting a decode signal as a write signal to the second memory. 2. 2. The multi-CPU system according to claim 1, wherein the read address signal is input, and a decode signal indicating an upper address of program data of the second CPU is output from the decoder, and an address signal passing through the bus buffer. 3. Is a lower address, and by combining the upper address and the lower address, an address of a second memory in which program data is to be stored is specified.