RU1807495C - Process-to-process interface - Google Patents

Abstract

The invention relates to computer technology and can be used in the construction of multi-machine complexes and multiprocessor systems. The purpose of the invention is to expand the functionality by simultaneously transmitting information simultaneously to several processors. The goal is achieved in that the device comprises from the first to the Nth switching units, where N is the number of switched processors of the system, the (N + +1) -th switching unit, and the control unit. 4 ill., 1 tab.

Description

The invention relates to digital computing and can be used in multi-machine computing systems for inter-machine communication.

, The purpose of the invention is the expansion of the scope of the device ..; In FIG. 1 is a structural diagram of the device of FIG. 2 is a functional diagram of a switching unit; in FIG. 3 is a functional diagram of a switching unit; in FIG. 4 is a functional diagram of a switching control unit; in FIG. 5 - algorithm of the device; in FIG. 6 is a timing diagram of the operation of the device.

The computer interface device (Fig. 1) comprises N interface units 11-1, a control unit 2, comprising a switching control unit 3 and. interface unit 4, local buses 5i-5r i for connecting to a computer, and system buses 6 for connecting a host computer. The II-IN units are connected via the address, control and data bus 6 to the control unit 3 and the interface unit 4.

The interface unit 1 (Fig. 2) contains an AND 7 element, AND-NOT elements 8, 9, a register 10, address decoders 11, 12, a counter. An OR-NOT element 14, a bi-directional data buffer 15, an AND 16 element, a trigger 17 , OR element 18, AND element 19, unidirectional data buffer 20, address decoder 21, OR element 22. Element AND 7, AND-NOT elements 8, 9, register 10, address decoders 11, 12, counter 13 and Trigger 17 are connected to the corresponding system buses 6, and the data buffer 15, the OR element 22, the data buffer 20, the address decoder 21 and the outputs of the register 10 are connected to the corresponding local buses 5.

The interface unit 4 (Fig. 3) contains AND elements 23, 24, AND-NOT elements 25, 26, register 27, address decoder 28, counter 29, AND-NOT elements 30, 31, bidirectional data buffer 32, OR 33 elements , 34, element And 35, unidirectional buffer givenO x |

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36. Elements 23-26, register 27, address decoder 28, counter 29 are connected to the corresponding buses of the host computer, and elements 30, 31, the data buffer 32, elements 34, 35 and the data buffer 36 are connected to the corresponding buses 6. Control node switching (Fig. 4) contains a read only memory (ROM) 37, register 38, ROM 39, address decoder 40, counter 41. The outputs of register 38 are connected to the inputs of ROM 37, 39, address decoder 40 is connected to the input of counter 41. Device for interfacing a computer through local buses 5 and system buses b it is connected to a group of computers between which It is necessary to realize the exchange of information.

The device operates as follows.

The device provides two modes of operation:

- information transfer from system buses 6 in parallel to all local buses 5 to which computer receivers are connected, and information transfer is carried out in the mode of direct access to the memory of both the transmitting and receiving computers:

- transmitting information in direct memory access mode from one of the local buses 5 in parallel to all other local buses 5 and, in addition, to the system buses 6.

The first mode of operation is implemented by the following sequence:

1. The computer through the system buses 6 loads the starting address of the memory in which the information for transmission is located into the counter 29 of the switching unit 4.

2. The computer through the system buses 6 sequentially loads the start addresses into the counters 13 of the necessary glare 1 of the pairing connected via the local buses 5 to the computer receivers.

3. Each block 1 of the interface through the bus 6 is configured to record information in the memory of the computer receiver.

4. The node 4 of the interface through the bus 6 is configured to read the array of information from the memory of the computer transmitter.

5. The number of bytes of the transmitted information array is recorded via the bus 6 to the counter 41 of the switching control unit 3.

6. Information exchange control is transferred to the switching control unit 3, which sets the CAPTURE signal to the control system buses 6, puts the computer transmitter processor into the third state and takes care of the exchange organization (operation logic is illustrated in Figs. 5 and 6).

7. After the end of the exchange (that is, when the content of the counter 41 of the switching control unit 3 becomes equal to zero), the CAPTURE signal is removed and the computer transmitter issues 5 commands via blocks 1. Run the functional program and then continues to execute its program.

After receiving a message about completion of the program with 0 information transmitted earlier by receiving the corresponding signals, Interrupt request to the system buses 6c of local buses 5 through address decoder 21 and trigger 17, which controls the computer via buses 6, starts preparing 5 information exchange between local buses in accordance with the necessary algorithm sharing. :

The host computer determines the computer transmitter and the computer receivers and conducts: .0 1. Download the starting address of the location. information in block 1, connected to a computer transmitter and setting it to read mode.

2. Downloading the start addresses in all 5 blocks of 1 pairing, which will be connected to the computer receivers, and setting them to the recording mode.

3. If it is necessary to write information in parallel through buses 6 to the system memory 0 of the control computer, similarly, it prepares the interface unit 4.

4. Writing to the counter 41 of the switching control unit 3 the length of the array of transmitted information.

5 After that, the switching control unit 3 provides parallel-fast information transfer between computers.

Let us dwell in detail on the operation of the interface unit 1 (Fig. 2).

0 Block 1 is configured from the host computer via system buses 6 by writing the required code to the register 10 according to the table. This table shows one of the 5 options for controlling the system.

If exchange functions are performed from the computer memory, the output of the OR element 22 generates a CAPTURE signal, which enters the computer. After receiving from the computer 0 signal Confirmation of capture (PZAHV) from bus 5, elements 7, 8 and buffers 15, 20 are prepared for operation.

In addition to loading register 10, before starting the exchange, the control computer loads into 5 counter 13 the starting address of the memory.

The exchange starts with the BOB signal (fast exchange). In this case, element 1/1 16 gives a permission signal to buffer 20, which connects the address from the output of Counter 13 to the local address line

bus 5, and to the buffer 15, which connects the data highway of the system 6 and the local bus 5. If information is recorded, the system signal Record .ZU (RAM memory) through the And 9 element will go to the local line of the RAM memory and at the same time, the buffer 15 will orient in the direction of the system data highway — the local data highway. If reading from bus 5 is performed, then the current signal of the read-only memory will be transmitted to the local line of the read-only memory via element 8. In both of these operations, the local READY line will be connected through valve 7 to the READY system line for analysis in mainframe computer.

A signal at input -1 of counter 13 is generated on the trailing edge of each pulse of the read-only memory or read-only memory, and each subsequent memory access is performed at the address in the following order. (Here it is taken into account that the address bus is inverse). This is provided by OR element 18 and AND element 19.

The flip-flop 17 and address decoder 21 enable the local computer to inform the host computer via the outputs of the bus 6 by means of the PROHIBIT signals about the completion of the current task.

Let us consider in detail the operation of the interface unit 4 (Fig. 3).

It is in many ways similar to the operation of the mating unit 1 described above.

The configuration of the interface unit 4 is carried out by the host computer by writing the required code to the register 27:

-....

In this case, the OR circuit 33 generates a resolving potential for the And circuit 24. In addition, the start address of the data array, which is read from or written to the memory, must be loaded into the counter 29. During the fast exchange controlled by the node 3, the BOB potential is generated by which the AND 24 circuit produces permission to pass the read-only memory signals through the I 25 circuit or the ST RAM through the I 26 circuit when reading or writing information. In addition, the output of AND circuit 24 enables the operation of the data buffer 32 and the address buffer 36.

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Claims (1)

After reading or writing another byte of information, one is subtracted from the contents of counter 29 (circuits 34 and 35). SUMMARY OF THE INVENTION A device for interfacing processors comprising a group of interfacing units, each of which contains two AND elements, two OR elements, an OR-NOT element, a register, three address decoders, bidirectional and unidirectional data buffers, a counter, a trigger, and information the control, addressing inputs and outputs of the first group of inputs and outputs of the 1st (1 1, .... N) interface unit are the device inputs and outputs of the same name, the information, control, addressing inputs and outputs of the second group of inputs outputs i-ro block sop through the system bus of the same name are connected to the same inputs and outputs of the second group of inputs and outputs of the (i + 1) -th interface unit, in each interface unit the output of the OR element is NOT connected to the first inverse input of the first AND element, the input of the first OR element , the outputs of the first and second bits of the register are connected respectively to the first and second inputs of the OR-NOT element, the output of the first address decoder is connected to the input of the register mode, the output of the second address decoder is connected to the counter mode input of the same name, the information in the moves of which are connected to the same input of a unidirectional data buffer, the output of the third bit of the register is connected to the reset reset input, the information input of which is connected to the output of the third address decoder, the output of the first element AND is connected to the enable input of the unidirectional data buffer, with the first input of the second the AND element with the enable input of the bi-directional data buffer, the output of the second OR element is connected to the second input of the second AND element, the output of which is connected to the counter input of the counter, the output is about the OR element, the outputs of the fourth, fifth, and sixth bits of the register, the outputs of the unidirectional data buffer are respectively the capture output, the first, second, and third outputs of the interrupt request, the output address of the first group of inputs / outputs of the interface unit, the write input of the external device of the first the input-output group of the interface unit is connected to the trigger synchronizing input, the address input of the first input unit group of the interface unit is connected to the input of the third address decoder, the first information inputs are bi-directional outputs data buffer connected to the information inputs and outputs of the first group of inputs and outputs of the interface unit, the address inputs of the second group of inputs and outputs of the interface unit are connected to the inputs of the first and second address decoders, system bi-directional information inputs and outputs of the second group of inputs and outputs of the voltage unit are connected to the second inputs and outputs of the bi-directional data buffer, with information inputs of the register, with information inputs of the counter, the trigger output is the request output of the second group of inputs of the interface unit; the recording input of the external device of the second group of inputs / outputs of the interface unit is connected to the synchronization inputs of the register and counter, characterized in that, in order to expand the scope by providing parallel transmission of the same type of information simultaneously to several computers, the composition control unit is introduced into it and a mating unit, and in each fading mate, a third AND element and two NAND elements; the switching control unit comprises two read-only memory blocks, a register, an address decoder, a counter; the interface node contains three AND elements; four AND-NOT elements, a bi-directional data buffer, a register, two OR elements, an address decoder, a counter, a unidirectional data buffer: in the control node, the output of the first permanent memory block is connected to the information input of the register, the output of which is connected to the address inputs of the first and the second permanent memory blocks, the first output of the address decoder of the control node is connected to the input of the first bit of the control address, the first constant memory block, the outputs of the address decoder are connected to the first information ion counter input, the first output of the second read-only memory block is connected to the counter input of the counter, the overflow output of which is connected to the input of the second bit of the address of the first read-only block, the inputs of the third, fourth and fifth bits of the address of the first read-only memory block, mode input register, the information input of the decoder, the second information input of the counter, the second-fifth outputs of the second read-only memory are respectively the recording inputs of the higher device, capture, ready in particular, requesting the address, data, write outputs, reading the exchange lock and capturing the group of inputs and outputs of the control unit, in the interface unit, the output of the first AND element is connected to the first inputs of the second AND element, the first and second AND elements, the third AND element, with the control input of the unidirectional data buffer, with the first control input of the bidirectional data buffer, the first output of the register is connected to the second input of the first NAND element, with the first input of the first element 0 OR, the second register output - with the second inputs of the second AND-NOT element and the first OR element, the output of which is connected to the first input of the first AND element, the output of the first AND-NOT element is connected to the output 5 of the third AND-NOT element, with the first input of the bi-directional data buffer switching control, with the first inverse input of the OR element, the output of the second element .. AND-NOT - with the output of the fourth element AND 0 NOT, with the second bi-directional data buffer switching control input, with the first the inverse input of the OR element, the output of which is connected to the second input of the third AND element, whose output is connected to the counter input of the counter, the second input of the first AND element is connected to the first inputs of the third and fourth elements AND NOT, the third input of the first element AND NOT - with the second input of the third element. 0 NAND, the third input of the second NAND element - with the third input of the third and second input of the fourth NAND element, the output of the address decoder is connected to the register mode input, the output group of the ad5 decoder is connected to the first group of counter information inputs, the second input of the second element AND, the outputs of the first and second elements AND NOT, the first information input-output of a bi-directional data buffer. 0 ny, the output of the unidirectional data buffer is, respectively, the ready input, read output, write output, data input-output, address output of the first group of input-output nodes 5 interfaces, the output of the second AND element, the inverse inputs of the first and fourth elements AND, the second information input-output of a bi-directional buffer, the input of the register mode and the input of the address decoder are the readiness output, the exchange interlock input, the read input, the write input. , data input-output, recording input of an external device and address input of the second group of inputs5 outputs of the interface unit of the interface unit, the output of the OR element is NOT connected to the first inverse inputs of the third AND element and the first and second element ntov AND-NO, the sixth discharge register output connected to a direct input of the first the AND gate, the output of the fifth category is with the direct input of the second AND gate, the output of the first AND gate is connected to the first input of the bi-directional data buffer switching control, with the first inverse input of the second OR gate, the output of the second AND gate NOT - with the second input of the bi-directional data buffer switching control and the second inverse input of the second OR element, the direct input of the third AND element, the outputs of the second and first AND elements, the third inverse input of the second AND element, respectively, are the readiness input, read output, write output and capture input of the first group by the input-output of the interface unit, the output of the third element And, the fourth inverse input of the second the NAND element, the third and the fourth inverse inputs of the first NAND element are, respectively, the ready output, the reads of the exchange interlock reading and the write of the second group of inputs and outputs of the interface unit, the information, control, address inputs and outputs of the second group of inputs -outputs of all blocks of the interface via the system bus are connected to the inputs and outputs of the same name input / output groups of the control unit and with the same inputs and outputs of the first the input / output groups of the interface node, the information control addressable inputs, the outputs of the second input / output group of the voltage node are the system inputs / outputs of the device for connecting the control processor. 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