JPH0681158B2 - Data transfer control device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device that is located between devices and that performs data transfer between devices with simple control and efficiently.

[Conventional technology]

Conventionally, when data is transferred between devices (hereinafter, the data sending side is abbreviated as “S side” and the data receiving side is abbreviated as “R side”), a register for temporarily storing transfer data between devices (hereinafter abbreviated as “register”) ) Is provided to solve the following problems.

When the S side should send data to the R side and the R side is performing another process and is not in a state to receive the data, the S side needs to wait for the data to be sent until the R side becomes ready to receive the data. Therefore, the performance of the S side is deteriorated.
Therefore, a register is provided between the devices, the S side stores the data to be transferred in the register, and thereafter, the S side performs the following processing and R
The side reads the stored data from the register at any time.

When the S side and the R side operate at independent clock timings, it is difficult to match the timing of data transmission / reception between both devices. Therefore, a register is provided between the devices, and data is transferred to the register by a data storage pulse from the S side. After that, the R side reads the data from the register at its own clock timing.

FIG. 2A is a circuit diagram of the conventional representative register described above. Explaining the circuit configuration of the register with reference to the figure, 21 is a flip-flop for temporarily storing data, 22 and 23 are 3-state gates, 24, 25, 27 and 28 are AND gates, 26 and 29 are OR gates, 20 is a circuit including all of the above, 30
Are NOT gates, 37, 38 are the same circuits as 20, 31, 32, 33 are data input / output lines with the device A side (device connected to the left side of the circuit diagram), and 34, 35, 36 are device B side ( Data input / output line with the device connected to the right side of the circuit diagram, 5 is a clock pulse input for storing the transfer data from the device A in the flip-flop group of the register, and 6 is the transfer data from the device B of the register. Clock pulse input for storing in the flip-flop group, 9 is an input for instructing the data transfer direction, data transfer from device A to device B when "1", device B when "0"
To device A.

Here, the operation of the register will be described with reference to FIG. Since the input 9 is "1" when the data is transferred from the device A side to the device B, the output of the NOT gate 30 becomes "0" and the outputs of the AND gates 24 and 27 become "0" and the output of the 3-state gate 23. Becomes high impedance. Therefore, 31 becomes an input, 31 and the data input D of the flip-flop 21, the clock pulse input 5 and the clock input C of the flip-flop 21.
And the output Q of the flip-flop 21 and the outputs Q and 34 of the flip-flop 21 are logically connected.

Similarly, when input 9 is set to “0”, 34 enters the input state and 34
And the data input D of the flip-flop 21, the clock pulse input 6 and the clock input C of the flip-flop 21 are logically connected, and 31 becomes an output and the flip-flop
Logically connected to the output Q of 21.

Further, FIG. 2 (b) shows a configuration in which the above register is provided between the devices. A conventional data transfer method between devices will be described with reference to FIG.

Consider a case where data is transferred from the device A to the device B (when the signal 9 is "1"). Device A has a register status flag (whether data is stored in the register,
Alternatively, the data transfer is controlled by a value indicating whether the flag is empty or realized by hardware or software, and if the value is OFF (the register is empty), the data to be transferred is set to the data bus 3, A clock pulse is added to the signal 5 to store the data in the register 2. If the value is ON (data is stored in the register), wait for data transfer until it is turned OFF. After the device A stores the data in the register 2, the register status flag in the device A is turned ON,
An interrupt to device B is generated at signal 41 to notify device B that the data has been stored in register 2.

In response to the interrupt from the device A, the device B turns on the register status flag in the device B indicating whether the register stores data or is empty like the device A. Thereafter, if this flag is ON, the process currently being executed is interrupted and the data on the data bus 4 is read, or the data currently being executed is completed and then the data on the data bus 4 is read. After the device B reads the data from the register 2, it turns off the register status flag in the device B and sends a signal to notify the device A that the data in the register 2 has been read.
At 42, an interrupt to device A is generated.

The device A receives the interrupt from the device B, turns on the register status flag in the device A, and repeats the above-described operation thereafter.

When data is transferred from the device B to the device A, the signal 9 is set to "0", the device B performs the processing of the device A described above,
The processing of the device B may be performed by the device A.

[Problems to be solved by the invention]

As described above, in the conventional technique, both the device on the data sending side and the device on the data receiving side have a flag indicating the state of the register, and a function of controlling the flag and a function of detecting an interrupt from the partner device are required. Since complicated software or hardware is required to realize these functions, the transfer efficiency cannot be improved when realized by software, and the device cost becomes high when realized by hardware.

The present invention has been made to remedy the above-mentioned drawbacks of the prior art, and its purpose is to provide a simple control and a simple circuit configuration, which is located between two devices, and which is located between these devices. An object is to provide a data transfer control device that efficiently transfers data.

[Means for solving problems]

To achieve the above object, in the present invention, a register is interposed between the first device and the second device, and when data is transferred from the first device to the second device through the register, the first device is used. A signal for storing transfer data from the first device to the register as the first signal,
After that, when the second device reads the transfer data from the register, the second device outputs a signal indicating that as the second signal, and the second device outputs the signal indicating the fact as the second signal. When transferring data to the register, the second device outputs, as the second signal, a signal for storing transfer data from the second device to the register, and then the first device outputs the signal. When the transfer data is read from the first device, the first device outputs a signal indicating that as the first signal. In the data transfer control device, the first signal and the second signal are branched and input. ,
A flip-flop is provided as a binary counter that is preset by either one of them and cleared by the other.

[Action]

The count output of the flip-flop is used as a transfer control signal for each of the first and second devices.

The control device according to the present invention is different from the prior art in that it is not necessary to provide means for displaying the state of the register in each device in the device, the interrupt function from the other device is not required, and the data transfer control is simple. It is different in that it can be realized with a hardware configuration and simple control.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, 1 is a control device according to the present invention, 2 is a register shown in FIG. 2 (a) which has already been described, 3 is a bidirectional data bus connected to the device A, 4 is bidirectional connected to the device B The operation modes of the data bus and the signals 5, 6, 7, 8 are as summarized in Table 1. 9 is an input indicating the data transfer direction and is "1"
In the case of, the device A to the device B, and in the case of "0", the device B to the device A. 10 is an input for initializing the control device 1 when "1" is input, 11 is a flip-flop (counter) indicating the state of the register, 12 and 13 are OR gates, 14 and 15 are AND gates, 16 is a NOT gate, Is.

Next, the operation of the embodiment shown in FIG. 1 will be described.

When data is transferred from device A to device B (signal 9 is "1") Since signal 9 is "1", 3 is input, 4 is output, and AN
The output of the D gate 14 becomes "0". Then flip-flop 1
A clock pulse is applied to signal 10 to initialize 1. As a result, the flip-flop 11 is cleared by inputting a clock pulse to the clear terminal CL via the OR gate 13, and as a result, the signal 8 becomes "0" and the signal 7 becomes "1".

Next, the device A transfers the data transferred to the device B to the data bus 3 by the signal 7 being "1" (the register 2 is empty).
Set on and add clock pulse to signal 5. As a result, the flip-flop 11 is preset by inputting a clock pulse to the preset terminal P via the OR gate 12, and as a result, the signal 8 becomes "1" and the signal 7 becomes "0".

Next, since the signal B of the device B is "1" (data is stored in the register 2), the data bus 4 can be input at any time.
The above data is read and the clock pulse is input to the signal 6. As a result, the flip-flop 11 receives the clock pulse at the clear terminal CL via the OR gate 13, and as a result, the signal 8 becomes "0" and the signal 7 becomes "1".

Similarly to the above, the device A is the device B if the signal 7 is "1".
Data to be transferred is set on the data bus 3 and a clock pulse is added to the signal 5. If the signal 8 is "1", the device B can read data on the data bus 4 and add a clock pulse to the signal 6 to transfer data from the device A to the device B.

When data is transferred from device B to device A (signal 9 is "0") Since signal 9 is "0", 3 is output, 4 is input, and AN
The output of the D gate 15 is always "0". Next, a clock pulse is applied to the signal 10 to initialize the flip-flop 11. As a result, the flip-flop 11 becomes an AND gate 1.
4, a clock pulse is input to the preset terminal P via the OR gate 12, and as a result, the signal is preset and the signal 8 becomes "1" and the signal 7 becomes "0".

Next, the device B sets the transfer data to the device A on the data bus 4 and adds the clock pulse to the signal 6 because the signal 8 is "1" (the register 2 is empty). As a result, the flip-flop 11 is cleared via the OR gate 13.
A clock pulse is input to CL to be cleared, and as a result, the signal 7 becomes "1" and the signal 8 becomes "0".

Next, since the signal A is "1" (data is stored in the register 2) in the device A, the data bus 3 can be used at any time.
The above data is read and a clock pulse is input to the signal 5. As a result, the flip-flop 11 is preset by inputting a clock pulse to the preset terminal P via the OR gate 12, and as a result, the signal 7 becomes "0" and the signal 8 becomes "1".
become.

Thereafter, similarly to the above, the device B is the device A if the signal 8 is "1"
Data to be transferred is set on the data bus 4 and a clock pulse is added to the signal 6. If the signal 7 is "1", the device A can read the data on the data bus 3 and add a clock pulse to the signal 5 to transfer the data from the device B to the device A.

〔The invention's effect〕

As described above, according to the present invention, control of data transfer between a register and each device is performed by a control device that is located between devices that perform data transfer via the register. There is an advantage that required control functions can be realized with a simple control circuit configuration.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 (a).
Is a circuit configuration diagram of a register used for transfer, and FIG. 2B is a block diagram showing a conventional data transfer control device. DESCRIPTION OF SYMBOLS 1 ... Control device according to the present invention, 2 ... Register for temporarily storing transfer data, 3, 4 ... Data bus (bidirectional),
5,6,9,10 …… Input signal line, 7,8 …… Output signal line, 11 ……
Flip-flop, 12,13 …… OR gate, 14,15 …… AND
Gate, 16 …… NOT gate, 21 …… Flip-flop, 2
2,23 …… 3-state gate, 24,25,27,28 …… AND gate, 26,29 …… OR gate, 30 …… NOT gate, 31-36 ……
Data input / output lines, 41, 42 ... Signal lines between devices.

Claims (1)

[Claims] 1. A register is interposed between a first device and a second device, and when data is transferred from the first device to the second device through the register, the first device first transfers the data. As a signal of 1, a signal for storing transfer data from the first device is output to the register, and then, when the second device reads the transfer data from the register, the second device outputs the second data. As a signal, output a signal indicating that,
When data is transferred from the second device to the first device via the register, a transfer data is stored from the second device to the register as the second signal from the second device. In a data transfer control device, which outputs a signal, and thereafter, when the first device reads the transfer data from the register, the first device outputs a signal indicating that as the first signal, A flip-flop is provided as a binary counter which is branched and inputted with the first signal and the second signal and which is preset by one of them and cleared by the other, and the count output of the flip-flop is used for the first and second signals. Two
And a data transfer control device for use as a transfer control signal for each device.