JPH053023B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a serial interface circuit that is built into a microcomputer or the like and performs serial data input/output with an external device (another computer or peripheral device) under the control of a CPU. [Prior Art] FIG. 5 is a block diagram showing the configuration of a conventional example of this type of serial interface circuit, FIG. 6 is a timing chart of this conventional example, and FIGS. FIG. 3 is a diagram showing a connection form between built-in single-chip microcomputers. The shift register 38 consists of eight D-type flip-flops 3 to 10, and when receiving data, it synchronizes serial data input from the outside via the input terminal SI and the input buffer 1 with the driving clock signal φ1 (output of the NOR gate 17). After receiving the 8-bit data, it is sent to the internal bus 20 according to instructions from the CPU (not shown). Also, when sending data,
It receives parallel data sent via internal bus 20, sequentially transfers it as serial data in synchronization with clock signal φ1, and outputs it from output terminal SO via data latch 36 and output buffer 2. The clock counter 18 counts the number of pulses of the driving clock signal φ1 of the shift register 38 during data transmission/reception, and outputs an interrupt signal f at the eighth count.
Outputs and resets the count value. The flip-flop 19 is set by the start signal g input from the CPU at the time of transmission, and is set by the interrupt signal f.
It is reset by The output buffer 14 is turned on when transmitting and outputs the inverted clock signal 1, and is turned off when receiving. nand gate 15
is the internal clock signal CK1 and flip-flop 1.
It inputs the Q output of 9 and outputs an inverted clock signal 1 of the internal clock signal CK1 via the output buffer 14 during transmission. The NOR gate 17 receives the external clock signal a that has arrived from the outside via the clock terminal during reception, and receives the inverted clock signal output from the output buffer 14 during transmission.
It inputs CK1 and outputs the drive clock signal φ1 for the shift register in either case. When the flip-flop 19 is reset by the interrupt signal f, the NOR gate 17 inputs a signal obtained by inverting its Q output by the inverter 16, holds the output at a low level, and stops outputting the drive clock signal φ1. Output control circuit 11, clock control circuit 1
2 controls on/off of the output buffer 2 and the output buffer 14, respectively, according to instructions from the CPU.
The input terminal SI, the output terminal SO, and the clock terminal are all connected to the internal bus 20, and their logic levels can be read by the CP at any time. Next, the operation of this serial interface circuit will be explained. (1) When receiving data First, the output control circuit 11 and clock control circuit 12 receive data sent via the internal bus 20.
Output buffer 2, 1 according to instructions from CPU
4 are respectively turned off. Next, a high level start signal g is input to the set terminal S of the flip-flop 19, and the flip-flop 19
The Q output of becomes high level. In this state, the external clock signal a is input to the clock terminal, and the 8-bit input data c is input to the input terminal SI. Then, the driving clock signal φ1 is outputted from the NOR gate 17, and the D-type flip-flops 3 to 10 receive the external clock signal a.
rising edge (falling edge of clock signal φ1)
The D input is latched in synchronization with the clock signal φ1, and this data is held when the clock signal φ1 is at low level. At the falling edge of the external clock signal a (rising edge of the clock signal φ1), the Q output is transferred to the next stage flip-flop. 4 to 10 and data latch 13, respectively, and data c is sequentially transferred. The clock counter 18 counts the number of rising and falling edges of the clock signal φ1, and resets the flip-flop 19 at the eighth falling edge. Then, the Q output of the flip-flop 19 is inverted and becomes a low level, and the driving clock signal φ ₁ from the NOR gate 17 is stopped, thereby stopping the data transfer of the shift register 38. On the other hand, the interrupt signal f output from the clock counter 18 is
When the CPU confirms this interrupt signal f, it reads the data of each D-type flip-flop 3 to 10 via the internal bus 20. Further, the level of external clock signal a from the clock terminal is fixed at high level. (2) At the time of data transmission First, transmission data sent via the internal bus 20 is set in each flip-flop 3-10 in parallel. Next, the output control circuit 11,
The clock control circuit 12 turns on the output buffers 2 and 14 according to instructions from the CPU, and a high-level start signal g is input to the set terminal S of the flip-flop 19. Then, the internal clock signal _CK1 is outputted from the clock terminal via the output buffer 14 to the outside, and is also input to the NOR gate 17, from which the drive clock signal _φ1 is outputted.
The D-type flip-flops 3 to 10 shift data in accordance with the drive clock signal φ ₁ synchronized with the rise of the internal clock signal CK ₁ , as in the case of the external clock a described above, and the data latch 36 shifts data according to the output of the D-type flip-flop 10. i
is the falling edge of the internal clock a of the clock terminal (the rising edge of the driving clock signal _φ1 )
This output data e is outputted via the output terminal SO. The clock counter 18 closes the flip-flop 19 at the eighth falling edge of the clock signal _φ1 , as in the case of reception.
and stops the transfer of the shift register 38. On the other hand, the interrupt signal f is sent to the CPU,
Completion of data transfer is confirmed. Further, the level of the clock terminal is fixed at high level. This serial interface circuit consists of two single-chip microcomputers 31a,
It is also possible to simultaneously transmit and receive data between three or more single-chip microcomputers 31c, 31d, . . . 31 (Fig. 7a).
It is also possible to transmit and receive data during the period e via the serial bus 32 (No. 7b). In the case of FIG. 7a, the output buffers 2 of the two single-chip microcomputers 31a and 31b are both conductive and transmit and receive data between them at the same time, and in the case of FIG. 7b, they are connected to the serial bus 32. Among the plurality of single-chip microcomputers 31c to 31e, the output buffer 2 of one computer is conductive and transmits data, and the output buffers 2 of the other computers are turned off and only receive data. . [Problems to be Solved by the Invention] The conventional serial interface circuit described above has no problems when continuously transmitting serial data stored in a shift register, but
One-bit data (ACK: The disadvantage is that an acknowledgment signal (acknowledge signal) cannot be output to the transmitting side. [Means for Solving the Problems] When receiving data, the serial interface circuit of the present invention sequentially receives serial data sent from the external device through the data input terminal in synchronization with a driving clock signal. A shift register that transfers the data input from the data bus to the data bus and serially outputs the data input from the data bus in synchronization with a driving clock signal during data transmission; A latch circuit that takes as input a signal separately sent via the control signal, selectively outputs one of the inputs under the control of the control signal, and can send the output to an external device via the data output terminal. have. [Function] In this way, by providing a data latch with a simple configuration and selectively outputting the output of the shift register and the data from the internal bus, it is possible to send an acknowledge signal from the internal bus after receiving data. I can do it. [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the serial interface circuit of the present invention, FIG. 2 is a circuit diagram showing the specific circuit configuration of the data latch 13 of this embodiment, and FIG. 3 is a circuit diagram of the present embodiment. This is a timing chart. In the serial interface circuit of this embodiment, instead of the data latch 36 in the conventional example shown in _FIG . ₂ , and the control signal (clock signal) φ ₁
Depending on the level of the control signal φ ₂ input separately from the CPU, the Q output in phase with the output i of the D-type flip-flop 10 is sent out, the previous state is maintained, and the internal bus 20
A data latch 13 is provided which performs three operations: sending out a Q output in phase with data h from the latches. As shown in FIG. 2, the data latch 13 includes transfer gates 21, 24, CMOS inverters 22, 23, 25, and PMOS transistors.
It consists of M ₁ and M ₂ and NMOS transistors M ₃ and M ₄ . In this data latch 13, when the control signal φ ₁ is “1” and the control signal φ ₂ is “0”, the transfer gate 21 is turned on, the input I ₁ is outputted via the CMOS inverters 22 and 23, and the control signal φ ₁ ,
When both _φ2 are “0”, CMOS inverter 2
2 and 25 operate to form a positive feedback loop to maintain the previous state, and when the control signal φ ₁ is “0” and the control signal φ ₂ is “1”, the transfer gate 24
is turned on, input I ₂ is connected to CMOS inverters 22 and 23
Output via . Table 1 is a logical table of the data rat 13 described above.

〔Effect of the invention〕

As explained above, the present invention takes the output of the shift register and the data from the internal bus as input, and by providing a data latch that can selectively output these, sends out an acknowledge signal via the internal bus after receiving the data. There is an effect that can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the serial interface circuit of the present invention, FIG. 2 is a circuit diagram showing a specific circuit configuration of the data latch 13 of FIG. 1, and FIG. Timing chart; FIG. 4 is a circuit diagram showing another circuit configuration of the data latch 13; FIG. 5 is a block diagram showing the configuration of a conventional serial interface circuit; FIG. 6 is a timing diagram of the conventional example shown in FIG. Figures 7a and 7b are diagrams showing how single-chip microcomputers each having a built-in serial interface circuit are connected to each other. 1...Input buffer, 2, 14...Output buffer, 3-10...D-type flip-flop, 11...
...Output control circuit, 12...Clock control circuit, 1
3...Data latch, 15...Nand gate, 1
6, 29, 34... Inverter, 17... Noah gate, 18... Clock counter, 19... Flip-flop, 20... Internal bus, 21, 24,
26, 27, 28, 33... Transfer gate, 22, 23, 25, 30, 31, 32...
CMOS inverter, M ₁ , M ₂ ... PMOS transistor, M ₃ , M ₄ ... NMOS transistor, SI...
...Input terminal, SO...Output terminal, ...Clock terminal, ACK...Acknowledge signal, _φ1 ...Control signal (clock signal), _φ2 ...Control signal, a...
...Clock signal input to the terminal, c...Input data of input terminal SI, e...Output data of output terminal _SO6 f...Interrupt signal, g...Start signal, h...Acknowledge signal from internal bus, i
...Output of the D-type flip-flop 10.

Claims (1)

[Claims] 1 Built into a microcomputer, etc., a CPU
A serial interface circuit that inputs and outputs serial data with an external device under the control of the external device, and synchronizes the serial data sent from the external device via the data input terminal with a driving clock signal when receiving data. a shift register that sequentially accepts and transfers data onto a data bus, and outputs transmission data input from the data bus in series in synchronization with a driving clock signal during data transmission; It is possible to input a signal separately sent via the bus line under the control of the control signal, selectively output one of the inputs under the control of the control signal, and send the output to an external device via the data output terminal. A serial interface circuit with a latch circuit.