KR930002353B1 - Laser printer engine connection control data sending circuits - Google Patents

Abstract

The circuit for transmitting engine control data from a control unit to an engine unit of a laser printer utilizes standard transistor-transistor logic gates (TTL) to obtain high speed transmission ratio and to decrease load of a control unit. The circuit includes a transmission alarm state generator (16) for generating transmission alarm signal according to transmission state control signal, a data transmitter (22) connected between a control unit and an engine unit to convert parallel control data transmitted from a control unit to serial data, a clock signal generator (38) for counting frequency divided clock signal, and a transmission control unit (50) for generating data transmission end signal when count end signal is received from the clock signal generator.

Description

Laser printer engine connection control data transmission circuit

1 is a data transmission circuit according to the present invention

2 is an operational waveform diagram of each part of FIG.

* Explanation of symbols for the main parts of the drawings

16: transmission status alarm unit 22: data transmission unit

38: clock generator 50: transmission control unit

52: gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an engine connection data circuit of a laser printer, and more particularly, to a circuit for converting control data of a laser printer into a serial data and transmitting it to a printer engine by a simple hardware configuration by a standard transistor transistor logic gate.

In general, the controller and the engine in the laser printer are in a format for transmitting the state and control data of each other to the serial data. The control unit of the laser printer has a function of receiving a print data and a printer control destination from a stepper computer, controlling the laser printer, and transmitting some engine control data to the engine for printing. The engine of the laser printer inputs a print control command and print data from the controller and performs laser printing.

In the conventional laser printer connection data transmission circuit, a microprocessor having a serial transmission port and a parallel data input port is used to convert the connection data transmitted in parallel from the control unit into a serial and transmit the same to the engine. However, in the conventional circuit using the microcontroller as described above, the program load is generated by masking the data conversion program and the control program on the microcontroller, and the processing speed is reduced by processing the data by software. It was very difficult to fabricate ASIC using one chip microcontroller.

Accordingly, an object of the present invention is to provide a laser printer engine connection control data transmission cycle for transmitting engine connection data of a laser printer using a transistor-transistor logic that is used in general.

It is another object of the present invention to provide a circuit for easily converting an engine-connected data transfer circuit into an ASIC using only a transistor-transistor logic gate for law.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is an engine connection control data transmission circuit diagram according to the present invention, which is connected to a control unit (not shown), and is a transmission state control signal transmitted from the control unit. In response to the transmission alarm signal ( A transmission state alarm unit 16 generating

It is connected between the control unit and the engine unit and writes parallel control data transmitted from the control unit. Latch), and the transmission clock ( Is connected to a data transmission unit 22 for serial conversion transmission in response to an input, a clock generator 24 for generating a clock of a predetermined period, the clock generator 24, and a transmission state alarm unit 16,

Is connected to the transmission status alarm section 16 of the transmission status alarm section 16, and the transmission status alarm signal of the transmission status alarm section 16 A clock generator 38 which is operated by a signal output and divides and outputs the output of the clock generator 24 at the same time and counts the divided clocks and outputs a counting completion signal when a predetermined number is completed;

The transmission alarm signal of the transmission state alarm unit 10 is connected to the transmission state alarm unit 16 and the clock generator 38. Outputs a gating signal, and a data transfer completion signal (0) is generated by the count completion signal of the clock generator 38. And a transmission control unit 50 for blocking the gating signal;

It is connected to the output terminal of the clock generator 38 and the transmission control unit 50 and the divided clock of the clock generator 38 by the output of the gating signal of the transmission control unit 50 to the data transmission unit 22 And a gate 52 which transmits to the jin portion.

In the above configuration, the transmission state alarm unit 16 transmits the transmission state data (AD = 0) output from the control unit to the transmission state control signal ( Latches the signal of the transmission alarm signal ( ), And a latch (D flip-flop) 12 for outputting a) and two inverters 14 and 21 for inverting and outputting the output of the latch 12.

The data transmission unit 22 is connected to the data output terminal and the control signal terminal of the control unit and outputs parallel control data AD ₀ -AD ₇ output from the control unit to the control data recording signal ( Latches and transfer clock Is connected to a serial output shift register 10 for serial-converting and outputting an output terminal of the shift register 10. Is connected to an output of the latch 18 and the latch 18 for synchronous transfer by the input of the control data. It consists of the inverter 20 which drives as).

The clock generator 38 includes the oscillator 24 and the transmission state alarm signal ( Is connected between the output terminal and the output terminal of the oscillator 24 and the transmission state alarm signal ( When the signal is input, the flip-flop 26 and the NAND gate 28 generating a "low" signal for a predetermined time, the first control signal output from the NAND gate 28 and the inverted transmission calculation alarm signal ( The AND gate 32 for outputting the shift control signal to the shift register 16 and the output of the shift control signal of the AND gate 32, and divide the output of the oscillator 24 into two. Transmission clock ) Is reversed so that the transmission clock of the shift register 10 ( ) And two inverters 34 and 36 respectively transmitting to the engine unit.

Transmission control unit 50 is a transmission state alarm signal of the transmission state alarm unit 16 ( Inverter 42 gates the inverted output of flip-flop 40 by inputting three flip-flops 40, 46, and 48, which are preset by And an AND gate 44 to output a gating signal to the AND gate 52, and block the gating signal in response to an input of the counting completion signal RCO and at the same time a data transmission completion signal ( ) To output

2 is an operational waveform diagram of each part of FIG. 1, (A) is a waveform diagram of the oscillation clock of the oscillator 24, (B) is a data (DATA) output waveform diagram outputted from the control unit, and CMD is control data. , AD ₀ is the data LSB and indicates the transmission state even when the logic "H" is "on" (C) is a control data write signal (outputted from the control unit) (D) is a transmission state control signal ( (E) indicates the transmission state alarm signal of the latch 12 (). (F) is the transmission state alarm signal of the latch 12 ( ) Is an inverted signal. (G) is a first control signal output from the NAND gate 28, (H) is a transmission clock (CMDCLK) which is a two-division signal of the counter 30, and (I) is a transmission inverting (H). Clock ( )to be. (J) is the counting completion signal (RCO) of the counter 30, and (K), (L), (M), and (N) are outputs of three flip-flops 40, 46, 48, The double (L) signal is a transmission completion signal ( (N) is a gating signal.

Hereinafter, an example of the operation according to the present invention will be described in detail.

Now, the clock as shown in FIG. 2A is oscillated from the oscillator 24 and outputs control data CMD as shown in FIG. And at the same time as the light signal shown in FIG. ) Is outputted first, the 8-bit control data (CMD) Is latched to the shift register 10 by

As described above, when the 8-bit control data CMD is latched in the shift register 10, the controller outputs AD ₀ (LSB) as a logic " high " (H) to the second databis DATA. Output as shown in Fig. (B), and the transmission state control signal (Fig. ) Is inputted to the output terminal CK of the latch 12, the latch 12 transmits a transfer state control signal ( ) Is changed from "low" to "high" by latching the data (AD ₀ = H) that alarms the transmission status. Outputs a signal.

At this time, the transmission state alarm signal as shown in FIG. Signal is inputted to the AND gate 32 and inverted by the inverters 14 and 21 as shown in FIG. Are input to the input terminal D3 and the engine portion (not shown) of the latch circuit 26 respectively. ) Is latched to the output of the oscillator 24 to delay output. Therefore, the output of the NAND gate 28 transitions from logic "high" to logic "low" and outputs the output terminal Q1 of the latch circuit 26 so that the output terminal Q1 of the latch circuit 26 is also "low" from "low" as shown in FIG. High ".

Therefore, the counter 30 maintains a cleared state because the AND gate 32 outputs a logic “low” while the logic “low” is output from the output terminal Q1 of the latch circuit 26, and the shift is performed. The register 10 loads the control data CMD latched therein into the internal shift register. When the output of the output terminal Q1 of the latch circuit 20 is converted to "high", the second gate 32 is input to the clock terminal CLK by the AND gate 32 outputting a logic "high". By dividing the clock of FIG. 2 by two, the transmission clock as shown in FIG. ) Is output to the AND gate 52. At this time, the flip-flops 40, 46, and 48 are all preset when the output of the output terminal Q of the latch 12 is "low", and the output is logical "high" at each output terminal Q. .

Therefore, the AND gate 52 logically multiplies the logic " high " output from the output terminal Q of the flip-flop 48 and the transmission clock MDCLK output from the output terminal Q1 of the counter 30. Output like (H). At this time, the output of the AND gate 52 is inverted as shown in FIG. 2 by the inverters 34 and 36, and is output as the shift clock terminal SRCLK of the shift register 10 and the clock of the engine unit. .

From the inverter 34, the transmission clock as shown in FIG. ) Is outputted, the shift register 10 serially shifts the 8-bit parallel transmission data CMD stored therein and outputs it as shown in FIG. 2. That is, 8-bit parallel data is serially converted in synchronization with the shift clock of FIG. 2 and output to the output terminal Q _H. The data transferred in series from the shift register 10 is transmitted to the transmission clock by a latch 18 for inputting a signal of the inverter 34 to the clock terminal CLK. Inverted delay output in synchronization with The serial data output from the latch 18 is inverted by the inverter 20 and driven by the engine unit.

By the above operation, when the control data CMD loaded in the shift register 10 is serially converted and output to the engine unit, when the count of the clock of FIG. A signal as shown in FIG. 2 is output to the counting completion terminal RCO (RCO is a ripple carry-out terminal). That is, when eight outputs of the output terminal Q1 are output, the counting completion signal as shown in FIG. 2 (J) is output to the clocks of the input terminal P and the flip-flop 46 of the inverter 42 and the flip-flop 40. Input to terminal CLK. At this time, the flip-flop 40 is preset by the output " low " of the output son Q of the initial latch 12, and then the " low " (counting completion signal RCO) input to the terminal P is applied. In the counter 30, the signal T before the output is clocked and latched by the clock CMDCLK to output a signal as shown in FIG.

Accordingly, when the counting completion signal RCO is output from the counter 30, the latch circuit 40 inputs the signal NAND gate 44 to the NAND gate 44 as shown in FIG. 5 by the clock CMDCLK. . Therefore, the AND gate 44 logically multiplies the counting completion signal inverted to "low" by the inverter 42 and the output "low" of the output terminal Q of the flip-flop 40 to flip the logic "low". Input is made to the input terminal D of 46). At this time, the flip-flop 46 latches the " low " output of the AND gate 44 at the falling edge of the counting completion signal RCO to transmit a control signal of the data transmission completion signal as shown in FIG. A signal that transitions to "high" as in 2 degrees M is applied to the clock of the flip-flop 48.

When the output of the output terminal Q of the flip-flop 48 transitions from "low" to "high" as shown in FIG. 2 (M), the flip-flop 48 is inputted to the input terminal D. The signal is latched as shown in FIG. 2 to block the output signal of the AND gate 52. Therefore, when the 8-bit data is serialized and the transfer is completed, the flip-flop 48 disables the gate 52 to block the clock output for two minutes from the counter 30.

As described above, according to the present invention, the data transmission can be performed at high speed by transmitting a connection data transmission circuit for transmitting data from the control unit of the laser printer to the engine unit using only a simple logic gate. Load can be reduced and the system has an easy advantage.

Claims (3)

In a laser printer engine connection control data transmission circuit having a control unit and a printer engine unit, a transmission state control signal connected to the control unit and transmitted from the control unit ( In response to the transmission alarm signal ( Is connected between the control unit and the engine unit and writes parallel control data transmitted from the control unit. Latch), and the transmission clock ( Is connected to a data transmission unit 22 for serial conversion transmission in response to an input, a clock generator 24 for generating a predetermined cycle clock, the clock generator 24, and a transmission state alarm unit 16. Is connected to the transmission status alarm unit 16 of the transmission status alarm unit 16, and the transmission status alarm signal of the transmission status alarm unit 16 A clock generator 38 which is operated by a signal output and outputs the output of the clock generator 24 by a predetermined amount, and simultaneously counts the divided clocks and outputs a counting completion signal when a predetermined number is completed; It is connected to the alarm unit 16 and the clock generator 38, the transmission alarm signal of the transmission state alarm unit 10 ( Outputs a gating signal and inputs a control data transmission completion signal according to the count completion signal of the clock generator 38. ) Is connected to an output terminal of the transmission control unit 50 that blocks the gating signal, and an output terminal of the clock generation unit 38 and the transmission control unit 50 to generate the clock by outputting a gating signal of the transmission control unit 50. And a gate (52) for transmitting the divided clock of the unit (38) to the data transmission unit (22) and the engine unit. The transmission state control signal of claim 1, wherein the transmission state alarm unit 16 transmits the transmission state data output from the control unit. Latches the signal of the transmission alarm signal ( Laser printer engine connection control data transmission comprising: a latch (D flip-flop) 12 for outputting a) and two inverters 14 and 21 for inverting and outputting the output of the latch 12. Circuit. The control data recording signal (3) according to claim 1, wherein the data transmission unit (22) is connected to a data output terminal and a control signal terminal of the control unit to output parallel control data output from the control unit. Latch by the Is connected to the shift register 10 for serial-converting output by the < RTI ID = 0.0 >)< / RTI > and the output terminal of the shift register 10. Is connected to an output of the latch 18 and the latch 18 for synchronous transfer by the input of the control data. A laser printer engine connection control data transmission circuit, comprising: an inverter (20) for driving as a;