JPS61193255A - Operation method for high speed central processing unit - Google Patents

Abstract

PURPOSE:In comparison with using a high speed ROM, to contrive to conserve power consumption, save space and reduce costs by using a high speed RAM as program memory of a high speed CPU. CONSTITUTION:Operate a general purpose ROM 5 as program memory, and before starting the high speed CPU 1, select the address lines 14, 17, data lines 15, 19 and control lines 16, 19 of the control CPU 4 by the control circuit 3 and connect the high speed CPU 1 program from the general purpose ROM 5 to the high speed RAM 2. The control CPU 4, after completing transmission of the program shall be changed over to the select circuit 3 and the high speed CPU 1 address line 8, data line 10 and control line 12 shall be connected to the high speed RAM 8 via the address line 9, data line 11 and control line 13. Thereafter, the control CPU 4 through the control line 6 instruct the high speed CPU 1 to start, and the high speed CPU 1 can be operated with the high speed RAM 2 as program memory.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of operating a high-speed central processing unit for data processing.

2. Description of the Related Art The operating method of a conventional high-speed central processing unit will be explained with reference to FIG. 2. 101 is a high-speed central processing unit (C
This high-speed central processing unit has a high-speed ROM (read-only memory) 102 that can be accessed at high speed as a program memory, and an address line 103. data line 104
and are connected by a control line 105. Reference numeral 106 denotes a central processing unit for controlling the apparatus using the high-speed central processing unit 101, which manages and controls the apparatus as well as the central processing unit 101 through a control line 107. This control central processing unit 106 has a general-purpose ROM (read only memory) 108 as a program memory and an address line 109. data line 1
10 and a control line 111. This general-purpose RO
M108 does not require high-speed access unlike the high-speed ROM 102 because the control central processing unit 106 does not operate at such high speed.

The control central processing unit 106 operates using the general-purpose ROM 108 as a program memory, and the high-speed central processing unit 101
control and manage the operations of

Now, the control central processing unit 106 is the high-speed central processing unit 101.
When a startup instruction is issued to the high-speed central processing unit 101, the high-speed central processing unit 101 starts operating using the high-speed ROM 102 as a program memory.

Problems to be Solved by the Invention However, according to the above-mentioned conventional operating method, the high-speed central processing unit 101 operates at extremely high speed, from several tens of n5ecs to hundreds of n5ecs per instruction cycle. The high-speed ROM 102 needs to operate at several tens of n5ecs, and a commonly used general-purpose ROM cannot be used.

This not only increases power consumption, but also limits the memory size and makes it expensive.Therefore, there are problems such as the overall power consumption of the device increases, the space is expanded, and the cost increases. 0 Therefore, the present invention aims to eliminate the drawbacks of the above-mentioned conventional example, and is a high-speed central processing unit that can operate with low power consumption, save space, and reduce costs. A means for solving the central processing problem and a technical means of the present invention for solving the above-mentioned problems is to write the program of the high-speed central processing unit into the ROM, which is the program memory of the control central processing unit, and to execute this program. After the data is transferred from the ROM to a high-speed RAM, which is a program memory for the high-speed central processing unit, by the control central processing unit, the high-speed central processing unit is operated using the high-speed RAM as a program memory.

Therefore, according to the present invention, it is possible to use Fugetsu's ROM as a program memory without using a special high-speed ROM, resulting in overall reduction in power consumption, space saving, and
This has the effect of reducing costs.

Embodiment Hereinafter, one embodiment of the operating method of the high-speed central processing unit of the present invention will be described in detail with reference to the drawings. In Figure 1, 1
is a high-speed central processing unit (CPU).

2 is the high-speed R which is the program memory of the high-speed central processing unit.
AM (random access memory); 3 is a selection circuit; 4 is a control central processing unit (CPU); 1 program has been written.

The controlling central processing unit 4 is connected to the high speed central processing unit 1 and the selection circuit 3 by control lines 6 and 7. The high-speed central processing unit 1 and the selection circuit 3 and the selection circuit 3 and the high-speed RAM 2 are connected to address lines 8, 9 . Connected by data lines 1.0, 11 and control lines 12.13, control central processing unit 4 is connected to general-purpose ROM 5 and address lines 14. The control central processing unit 4 is connected to the selection circuit 3 and the address line 17 . They are connected by a data line 18 and a control line 19. Therefore, according to instructions from the control central processing unit 4, any of the address lines 8.17. Data line 10.
18 and control lines 12.19 and transfer them to address lines 9.18 and control lines 12.19. A data line 11 and a control line 13 allow connection to the high speed RAM 2.

The control central processing unit 4 operates using the general-purpose ROMg as a program memory, and before starting the high-speed central processing unit 1, the selection circuit 3 selects the control central processing unit 4O7)'res14, 17, data lines 16, 18, and control line 1
6.19 is selected to connect the program of the high-speed central processing unit 1 from the general-purpose ROM 6 to the high-speed RAM 2. After the program transfer is completed, the control central processing unit 4 switches the selection circuit 3 to select the address line 8. of the high speed central processing unit 1. Data line 1o and control line 12 are connected to address line 9. data line 1
1 and control line 13 to the high speed RAM 8. Thereafter, the control central processing unit 4 instructs the high speed central processing unit 1 to start up through the control line 6, and the high speed central processing unit 1 can operate the high speed RAM 2 as a program memory.

In this way, in this embodiment, since the high-speed RAM 2 is used as the program memory of the high-speed central processing unit 1, there is relatively no limit to the memory size even for high-speed operation.
Even if the program size is large, the total number of RAMs can be small, allowing for a space-saving configuration. Further, since the power consumption of a single ROM is lower than that of a high-speed ROM, and the total number of ROMs may be small, it is possible to reduce power consumption. Also,
Since the unit cost is low, the overall cost can be reduced. Furthermore, in this embodiment, a general-purpose ROM 5 is used as the program memory of the control central processing unit 4,
Since this general-purpose ROM does not require high-speed operation, a large capacity can be used. Therefore, by writing different programs in advance and changing the program to be transferred, different programs can be put into practice on the same hardware. be able to.

Effects of the Invention As is clear from the above description, according to the present invention, a high-speed RAM is used as the program memory of the high-speed central processing unit, and the program of the high-speed central processing unit is transferred from the program memory of the control central processing unit to the high-speed central processing unit. Before startup, the data is transferred to the high-speed RAM mentioned above, and the high-speed central processing unit transfers it to the high-speed RAM mentioned above.
M is made to operate as a program memory. Therefore, compared to conventionally using a high-speed ROM as a program memory for a high-speed central processing unit, it is possible to achieve lower power consumption, space saving, and lower cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the operating method of a high-speed central processing unit according to the present invention, and FIG. 2 is a block diagram showing an operating method of a conventional high-speed central processing unit. 1... High-speed central processing unit, 2... High-speed RAM, 3... Selection circuit, 4... Control central processing unit, 5...・General-purpose ROM. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (1)

[Claims] A program of the high-speed central processing unit is written in a ROM which is a program memory of the control central processing unit, and this program is transferred from the ROM by the central processing unit to a high-speed RAM which is a program memory for the control central processing unit. A method for operating a high-speed central processing unit, characterized in that the high-speed central processing unit is operated using the high-speed RAM as a program memory.