JPH03163671A - Image processor - Google Patents

Abstract

PURPOSE:To execute the image processing at a high speed by connecting and cutting off dynamically a system bus by a busdisconnecting means so that plural image memories can be brought to access simultaneously by plural CPUs. CONSTITUTION:A video signal obtained from a photographing system 5 is digitized by a signal processing circuit 6, and by an image input board 7, image data is stored in image memory boards 2a - 2c through a system bus 1. Subsequently, by reading the contents of the boards 2a - 2c by the corresponding CPU boards 3a - 3c, an image processing is executed. By switching on bus switches 4a - 4c provided on the bus system 1, the same image data is stored simultaneously in the image memories 2a - 2c through the bus 1. Next, by turning off the switches 4a - 4c, the bus 1 is divided into plural system buses 1a - 1c, the independent system buses are offered to the memory boards 2a - 2c and the CPUs 3a - 3c and the image processing can be executed in parallel.

Description

[Detailed Description of the Invention] [Summary] Regarding an image processing device in which a plurality of image memories and a plurality of CPUs use a common system bus, the plurality of CPUs simultaneously access the plurality of image memories to perform parallel processing,
Aiming at speeding up image processing, the system includes a plurality of image memories to which image data is supplied via a system bus, and predetermined processing for the image data loaded into the image memories using the system bus. and at least one bus switching means that is provided at one or more places on the system bus and connects or disconnects the system bus, and the bus switching means disconnects the system bus. Then, the image processing by the plurality of CPUs and image memories is executed in parallel.

[Industrial application field]

The present invention relates to an image processing apparatus, and particularly to an image processing apparatus in which a plurality of image memories and a plurality of CPUs use a common system bus.

With the spread of image media in recent years, it is required to process (recognize) large amounts of image data in a short time. Therefore, there is a demand for an image processing apparatus capable of high-speed processing.

[Prior Art] FIG. 8 is a block diagram showing an example of a conventional image processing device. As shown in the figure, the conventional image processing device
The analog video signal obtained from the imaging system 105 is digitized by the signal processing circuit 106, and the image human power board 10
7, image data is stored in the image memory boards 102a, 102b, and 102c via the system bus 101. And each image memory (board) 102a, 102b. When the image processing for 102c is completed, for example, the corresponding CPU (board)
Image processing is performed in a sequence in which the image memory boards LO2a, 102b, and 103c read the contents (image data) of the image memory boards LO2a, 102b, and 102c, and rewrite them if necessary.

(Problems to be Solved by the Invention) As described above, conventionally, the image processing apparatus shown in FIG.
02a, l02b, 102c and multiple CPU1
03a, 103b, and 103c.

However, this conventional image processing device has only one set of system buses for reading and writing image data.
No other CPU could use the system bus until one CPU finished accessing the image memory. That is, specifically, the image processing performed by the C P Ul03a by accessing the image memory IO2a, and the
If image processing performed by the CPU 103b by accessing the image memory 102b overlaps, for example, the CPU 103
If the priority of process b is low, system bus 10
1, the CPU 103a uses the image memory 102.
After the image processing that accesses the image memory l0 is completed, the CPU 103b uses the system bus 101 to access the image memory l0.
Image processing that accesses 2b will be executed.

Therefore, CPU 103a. LO3b103
c uses the system bus 101 to connect each image memory 102
There was a problem to be solved that image processing that accesses a, 102b, and 102c could not be executed in parallel, and that the speed of image processing could not be increased.

SUMMARY OF THE INVENTION In view of the above-mentioned problems with the conventional image processing apparatus, it is an object of the present invention to speed up image processing by allowing multiple CPUs to access multiple image memories at the same time to perform parallel processing.

[Means to solve the problem]

FIG. 1 is a block diagram showing the principle of the image processing apparatus according to the present invention.

According to the present invention, a plurality of image memories 2 to which image data is supplied via a system bus l;
A plurality of CPUs 3 perform predetermined processing on the image data taken into the image memory 2 using and at least one bus switching means 4 for interrupting the system bus 1 so that the image processing by the plurality of CPUs 3 and the image memory 2 is executed in parallel. An image processing device with features is provided.

[For production]

According to the image processing apparatus of the present invention, the bus switching means 4 provided at one or more locations on the system bus 1 shuts off a predetermined location on the system bus 1. This allows multiple CPUs to use the system bus 1, which is divided into multiple parts.
3 can simultaneously access a plurality of image memories 2 and execute predetermined processing in parallel.

That is, the image processing device of the present invention dynamically connects and disconnects the system bus to improve system bus usage efficiency and allows multiple CPUs to access multiple image memories at the same time. It is possible to perform parallel processing and speed up image processing.

C Embodiment] Hereinafter, embodiments of the image processing apparatus according to the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the image processing apparatus of the present invention. As shown in the figure, the image processing apparatus of this embodiment digitizes an analog video signal obtained from a photographing system 5 by a signal processing circuit 6, and converts it into a digital signal by an image input board 7.
The image memory board 2a,
Image data is stored in 2b and 2c. And each image memory (board) 2a, 2b.
When the image processing for 2c is completed, image processing is executed by, for example, the corresponding CPUs (boards) 3a3b, 3c reading the contents (image data) of the image memory boards 2a, 2b, 2c and rewriting them if necessary. That will happen.

The system bus 1 is provided with bus switchers 4a and 4b whose switching is controlled by the main CPU 3a, and the system bus 1 is connected and disconnected as necessary. In addition, this lotus switching i34a, 4
The switching command for b is sent to each CPU 3b,
Information such as the status of the path switchers 4a and 4b, that is, where the system bus 1 is connected and disconnected, is also supplied to the CPUs 3b and 3c.
However, it is possible to confirm.

Here, the images input to each image memory 2a, 2b, 2c may be, for example, the same image data, R (RED) image data, G (GR
Various image data can be input, such as EEN) image data, B (BLUE) image data, or a 1/3 partial image obtained by dividing one object into three equal parts.

For example, when performing multiple processes on the same image data, the bus switchers 4a, 4b are switched on and the same image data is transferred to the multiple image memories 2a, 2b, 2c via the system bus l. It is designed to simultaneously store both data and data at the same time. Thereafter, by switching off the bus switchers 4a and 4b, the system bus is divided into a plurality of system buses la, lb, and lc, and each image memory 2a, 2b, 2c and CPU 3a, 3b, 3
The system is configured to provide an independent system bus to c so that image processing can be executed in parallel.

3 and 4 are diagrams for explaining an example of the operation of the image processing apparatus shown in FIG. 2, and FIG. 5 is a diagram showing an example of processing in the image processing apparatus shown in FIG. 2. As is clear from FIGS. 3 and 4, the system bus 1 consists of an address bus 11, a data bus 12, and a control bus 13, with two path switches 41a and 42a for each bus 11, 12, and 13, respectively. , 43a and 4l
b, 42b, and 43b are provided.

As shown in FIG. 5, all image memories 2a, 2b
, 2c, bus switches i4a and 4b are switched on, that is, as shown in FIG.
2a, 43a and 4lb, 42b, 43b are connected, and the analog video signal obtained from the imaging system 5 is digitized by the signal processing circuit 6, and the image data signal supplied from the image human power board 7 is connected to the system bus 1. The image data is simultaneously written to each image memory 2a, 2b, 2c via the image memory 2a, 2b, 2c. In this way, after the image input processing for the plurality of image memories 2a, 2b, and 2c is executed, for example, C P [
J3a, 3b, 3c are each image memory 2a, 2b, 2
When image processing is performed in parallel by accessing the bus switch 4a and 4b, the bus switchers 4a and 4b are switched off, that is,
As shown in FIG. 4, bus switches 41a, 4
2a. 43a, 4lb, 42b, 43b are in a disconnected state, and each CPU 3a, 3b, 3c is disconnected and uses the independent system bus la, lb, lc to access the corresponding image memory 2a, 2b, 2c. It is designed to perform image processing. specifically,
For example, the CPU 3a accesses the image memory 2a via the blocked system bus 1a to perform predetermined image processing, and the CPU 3b accesses the image memory 2b via the blocked system bus lb to process other images. Processing is performed, and furthermore, CP03c connects the system bus 1c that has been cut off
The image memo 'J2c will be accessed via , and other image processing will be performed. Here, the switching of the lotus switch 4a and 4b is performed by a command from the main CPU 3a, and this switching command is issued by each CPU.
It is also supplied to U3b and 3c, and C P U3b and 3c confirm that the system bus I has been cut off by the bus switchers 4a and 4b, and change the usable state of the cut off system buses Ib and 1c to L'2. 76 It is done to cheat.

FIG. 6 is a diagram showing another example of the processing in the image processing apparatus of FIG. 2, and FIG. 7 is a diagram for explaining another example of the operation of the image processing apparatus of FIG. 2.

The process shown in FIG. 6 is performed after performing the same process as in FIG.
For example, the (preprocessed) image data that was first processed by the CPU 3c and stored in the image memory 2C is further processed by the CPU 3c.
When processing is performed by the CPU U3b, the bus switch 4b is switched on, and the image stored in the image memory 2c is accessed by the CPU 3b using the system buses 1b and 1c to perform image processing. There is. In this manner, the image processing apparatus of this embodiment can perform efficient image processing by independently controlling the switching of each bus switch 4a, 4b depending on the content of the processing. This embodiment can obtain processed results in a shorter time than when one CPU continuously performs image processing.

[Effects of the Invention] As explained above, according to the image processing device of the present invention,
Dynamically connect and disconnect the system bus to improve system bus usage efficiency and
The PU can access multiple image memories at the same time to perform parallel processing and execute image processing at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of an image processing device according to the present invention. FIG. 2 is a block diagram showing an embodiment of the image processing device according to the present invention. FIG. 3 and FIG. 4 are images of FIG. 2. 5 is a diagram for explaining an example of the operation of the processing device; FIG. 5 is a diagram illustrating an example of processing in the image processing device in FIG. 2; FIG. 6 is a diagram illustrating another example of processing in the image processing device in FIG. 2. FIG. 7 is a diagram for explaining another example of the operation of the image processing apparatus shown in FIG. 2, and FIG. 8 is a block diagram showing an example of the conventional image processing apparatus. (Explanation of symbols) 1... System bus, 2... Image memory, 2a. 2b, 2c...image memory board, 3...C
PtJ, 3a+3b+3c...- CPU board, 4... Bus switching means, 4a, 4b... Bus switching device, 5... Photographing system, 6... Signal processing circuit, 7... Image input board.

Claims (1)

[Claims] 1. A plurality of image memories (2) to which image data is supplied via a system bus (1); and a system for image data taken into the image memory using the system bus. Multiple CPUs that perform predetermined processing
(3) and at least one unit provided at one or more locations on the system bus for connecting or disconnecting the system bus.
and a bus switching means (4), wherein the system bus is cut off by the bus switching means so that image processing by the plurality of CPUs and image memories is executed in parallel. Device.