JP2687716B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is used for an information processing apparatus having a plurality of CPUs. In particular, it relates to data transfer means between CPUs.

〔Overview〕

According to the present invention, in a data transfer means that passes through a plurality of dual port memories of an information processing apparatus having a plurality of CPUs, transfer control is performed by using a direct memory access control unit so that data transfer between CPUs can be performed. This is to improve efficiency.

[Conventional technology]

FIG. 3 shows a conventional example. The CPU 31 can access the DPM 33 and DPM 34, and the CPU 32 can access the DPM 34 and DPM 35. The CPU 31, DPM 33, and DPM 34 are connected by one data bus, and the CPU 32, DPM 34, and DPM 35 are connected by another bus. Where CPU37 and C
When attempting to copy the data written in the DPM 33 to the DPM 35 for communication with the PU 38, first, the program of the CPU 31 causes the data of the DPM 33 to be read and written in the DPM 34. In addition, DPM34 by the program of CPU32
The data written in is written in DPM35. This 2
The data transfer is completed through the step sequence. Also, CPU32
Before starting copying data from DPM34 to DPM35, CP
It is necessary to confirm through the data written in DPM34 that U31 has completed the data transfer from DPM33 to DPM34.

[Problems to be solved by the invention]

As described above, in the conventional example, when trying to communicate between CPUs that are separated from each other due to the configuration of the data bus, many software procedures are required, and especially when there is a lot of data to be transferred, a long time is required. In addition, there is a drawback that the processing of the CPU existing on the way is stopped for a long time. Therefore, in a system in which data is frequently exchanged among a plurality of CPUs, the performance of the entire system would be significantly reduced.

The present invention eliminates such drawbacks, and an object of the present invention is to provide an information processing apparatus capable of efficient data transfer.

[Means for solving the problem]

A first aspect of the present invention is to connect three dual-port memories inserted in a data bus whose both ends are open and a data bus between both ends of the data bus and adjacent dual-port memories. In an information processing device including four CPUs, the data transferred in the order of adjacency via the dual port memory,
Data transfer between adjacent dual port memories is performed after a short time according to the request of two CPUs connected to the data bus connecting these three adjacent dual port memories among the above four CPUs. It is characterized in that it is provided with one direct memory access control unit for controlling as described above.

A second aspect of the present invention is a plurality of dual port memories inserted into a data bus whose both ends are closed, and a plurality of dual port memories connected between adjacent dual port memories. In an information processing device equipped with a CPU, for data transfer via a plurality of adjacent dual-port memories, data transfer between adjacent dual-port memories may be reduced in response to a request from all of the plurality of CPUs. It is characterized in that it is provided with one direct memory access control unit for performing control so as to wait for a while.

[Action]

In these two inventions, the data transfer via the dual port memory is performed by the CPU requiring many software procedures.
Instead of the control by the control by the direct memory access control means, the control is performed by the direct memory access control means to realize quick data transfer. In particular, according to the second aspect of the present invention, during the transfer by the direct memory access control means, it is possible to execute the data transfer via one dual port memory on the other detour path.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention.

In this first embodiment, as shown in FIG. 1, dual port memories 3, 4 and 5 inserted in a data bus,
CPUs 1 and 2 connected to a data bus between adjacent dual port memories, and CPUs 7 and 8 connected to both ends of the data bus, respectively. Further, as a feature of the present invention, the data bus is provided. Is a structure in which both ends thereof are open, and a direct memory for controlling the transfer of the data transferred in the order of its adjacency via the dual port memories 3, 4 and 5 in response to the requests of the CPUs 1 and 2. The access control unit 6 is provided.

 Next, the operation of this first embodiment will be described.

Here, a case where data is transferred from the CPU 7 to the CPU 8 will be described as an example. First, the CPU7 sends information indicating that the CPU1 and the CPU2 will transfer data to the CPU8 to the DPM3 and DPM4.
Tell through. Since this information itself requires a small amount of information, this transmission is completed in a short time. Next, what is CPU1 and CPU2
Before performing data transfer from DPM3 to DPM5, each individual process is temporarily stopped. At this stage, CPU1 and CPU2 are DP
Enter data transfer procedure from M3 to DPM5, DMA to DMAC6
Give transfer request information. When the DMAC6 receives DMA requests from both CPUs 1 and 2, it stops the operations of CPU1 and CPU2, and then starts the memory-to-memory transfer from DPM3 to DPM4 one word at a time (the number of bits for the data bus width). , After a slight delay, the memory transfer from DPM4 to DPM5 is started. When the necessary amount of information has been transferred from DPM3 to DPM4, and further from DPM4 to DPM5, DMAC6 relinquishes the data bus to CPU1 and CPU2 and ends the DMA transfer. After this CPU8
Reads the contents of DPM5 and completes the data transfer from CPU7 to CPU8.

The DMA transfer does not involve software to move the CPU, and the CPU does not need time to access the ROM or RAM, so it is possible to perform extremely high-speed data transfer determined by the DPM access speed. Figure 4 shows DPM3 to DP
The time required to transfer information up to M5 is shown in comparison between the case of the multiprocessor system according to the present invention and the case of the prior art. In the figure, (a) and (c) are the time required to transfer information from DPM3 to DPM4, and (b) and (d) are from DPM4.
The time required for information transfer to the DPM 5 is shown, (a) and (b) according to the present invention, and (c) and (d) according to the prior art.

FIG. 2 is a block diagram showing the configuration of the second embodiment of the present invention.

In this second embodiment, as shown in FIG. 2, dual port memories 11, 12, 13 and 14 inserted in the data bus are provided.
And CPUs 21, 22, 23 and 24 connected to the data bus between the adjacent dual port memories, and as a feature of the present invention, the data bus has a configuration in which both ends are closed. The direct memory access control unit 20 controls data transfer via a plurality of adjacent dual port memories in response to requests from all the CPUs 21, 22, 23 and 24.

 Next, the operation of the second embodiment will be described.

Here, a case where data is transferred from the CPU 21 to the CPU 23 will be described as an example. First, CPU21
Information about data transfer to the CPU23 is displayed on the DPM12 and DPM13.
Tell through. Since this information itself requires a small amount of information, this transmission is completed in a short time. Next, the CPU 22 temporarily stops each individual process before data transfer from the DPM 12 to the DPM 13. At this stage, the CPU 22 enters a data transfer procedure to the DPM 13 and gives DMA transfer request information to the DMAC 20. When the DMAC20 receives the DMA request from the CPU22, the CPU22
Then, the memory transfer from DPM12 to DPM13 is started word by word (the number of bits corresponding to the data bus width). When the required amount of information has been transferred from DPM12 to DPM13,
The DMAC 20 yields the data bus to the CPU 22 again, and ends the DMA transfer. After this, CPU23 reads the contents of DPM13, and CPU2
Data transfer from 1 to CPU 23 is completed.

Also, by utilizing the fact that the buses are connected in a ring shape, while transferring information from CPU21 to CPU23 using the above DMA transfer, at the same time, CPU21 and CPU24 via DPM11
Between the CPU 23 and the CPU 24 via the DPM 14 can also be performed.

The DMA transfer does not involve software for operating the CPU, and the CPU does not need time to access the ROM or RAM, so it is possible to perform extremely high-speed data transfer determined by the access speed of DPM.

〔The invention's effect〕

As described above, since the present invention includes the direct memory access control unit that controls the data transfer between DPMs, by performing DMA transfer between DPMs almost simultaneously, a large amount of data can be transferred between multiple CPUs at high speed. It is possible to perform transfer, and it is possible to perform high-performance and advanced information processing with little performance deterioration due to communication between CPUs.

[Brief description of the drawings]

FIG. 1 is a block diagram of the first embodiment of the present invention. FIG. 2 is a block diagram of the second embodiment of the present invention. FIG. 3 is a block diagram of a conventional example. FIG. 4 is a diagram showing a comparison between the conventional example and the example regarding the information transfer time. 1, 2, 7, 8, 21-24, 31, 32, 37, 38 ... CPU, 3,
4, 5, 11-14, 33, 34, 35 ... Dual port memory (DPM), 6, 20 ... Direct memory access control unit (D
MAC).

Claims (2)

(57) [Claims] 1. A dual-port memory inserted into a data bus whose both ends are open, and four CPUs connected to both ends of the data bus and a data bus between adjacent dual-port memories, respectively. In the information processing apparatus including the above, regarding the data transferred in the order of adjacency via the dual port memory, the data connected to the data bus connecting the three adjacent dual port memories of the four CPUs An information processing device comprising one direct memory access control unit for controlling data transfer between adjacent dual-port memories so as to wait a short time in response to a request from one CPU. 2. Information comprising a plurality of three or more dual port memories inserted in a data bus whose both ends are closed, and a plurality of CPUs connected to the data bus between adjacent dual port memories. Regarding the data transfer via the multiple dual port memories adjacent to each other in the processing device, the data transfer between the adjacent dual port memories should be performed after a short time in response to the request from all of the above multiple CPUs. An information processing device comprising one direct memory access control unit for controlling the above.