JPH04209059A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To minimize the occupation time of respective devices at a transfer origin and a transfer destination and to improve the throughput of the whole system by performing a read cycle and a write cycle in a batch. CONSTITUTION:A direct memory access(DMA) device 2 outputs a transfer source address to the transfer source device through a transfer source address control circuit 211 and a DMA control circuit 211 sends a data read signal to the transfer destination device at the same time. At this time, an internal address control circuit 217 outputs the storage addresses of transfer source data to an internal storage device 214. After they are all stored, the circuit 211 sends a data write signal to the transfer destination device. An internal address control circuit 218 outputs the storage addresses of data sent out to the device 214. Consequently, the contents of the device 214 are transferred to the data storage locations of the transfer destination device. Thus, the read cycle and write cycle are carried out in a batch.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates generally to direct memory access (DMA) controllers, and more particularly to direct memory access (DMA) controllers, and more particularly to The present invention relates to a device that transfers data between storage devices or between different storage areas within a main storage device via a CPU.

[Conventional technology]

FIG. 2 shows a system configuration diagram using a DMA device. (
1) is the central information processing unit (CPU), +21 is the direct memory access device ff1l (DMA#Afl!)
, +31 is a main storage device, (4) is an input device, (5) is an output device, (6) is a data bus, (7) is an address bus, and (8) is a side bus. The beginning of the sentence) is the main memory (3)
is the transfer source storage area, and Z is the transfer destination storage area in the main storage device (3). Input device (4) and output device (5)
The location to be accessed is specified by addressing from the address bus (7).

During DMA transfer, the input device (4) or main storage device (
The source storage area t311 in 3) is the source device, the source storage area t311 in the output device (5) or the main storage device (3)
The three devices serve as transfer destination devices.

Normal data transfer is performed by the CPU that has acquired the right to use the bus.
(1) is performed using a system bus consisting of a data bus (6), an address bus (7), and a control bus (8).

Data transfer by the DMA device (2) is performed by the CPU (1).
+, After the bus usage right is arbitrated between the DMA devices (2) and the DMA device (2) acquires the bus usage right and becomes the bus master, the DMA device (2) uses the system bus to .

FIG. 3 shows an internal configuration diagram of a conventional DMA device (2).

(221) is a DMA I1II control circuit, (222) is a transfer source address control circuit, (223) is a transfer destination address circuit, and (224) is a temporary register. Also (6)
is a data bus, (7) is an address bus, and +81 is a control bus, which are the same as those shown in FIG.

The transfer operation of the conventional DMA device (2) will be described below.

Upon accepting the request for DMA operation, the DMA device i 12
1 requests the CPUtl+ for the right to use the bus.

When the bus is released by CPU (1) and the right to use the bus is acquired, DMA device 1 (2+ enters DMA operation. DM
At the beginning of operation A, the DMA device t 121 outputs the transfer source address to the transfer source device through the transfer source address control circuit (222), and at the same time outputs the transfer source address to the transfer source device through the transfer source address control circuit (222).
A data read signal is sent to the transfer source device 11 through the control bus (8). As a result, the transfer source data is transferred to the temporary register (224) in the DMA device (2) (read cycle). Next, the DMA device t +21
At the same time as outputting the transfer destination address to the transfer destination device through the transfer destination address control circuit (223), the DMA control circuit (221) sends a data write signal to the transfer destination device via the control bus (8). As a result, the contents of the temporary register (224) are transferred to the transfer destination address control circuit (223).
The data is transferred to the data storage location of the destination device specified by (write cycle). The data size of the temporary register (224) is usually the same as the size of the data bus (6). Therefore, for n times the data transfer of the data bus (6), n read cycles and write cycles are executed to complete the DMA transfer. FIG. 4 shows the DMA operation flow of the conventional device.

Further, when transferring one transfer source data corresponding to the size of the data bus to a plurality of transfer destinations, the flow is performed as shown in FIG. 6 by fixing the address of the transfer source address control circuit (222).

In this case as well, it is necessary to execute n read cycles and write cycles to a transfer destination that is n times the size of the data bus (6).

Further, the temporary register (224) is a temporary storage means only for holding data during a read cycle until a write cycle, and operations such as inverting data or performing arithmetic processing with a certain value between read and write cycles are not allowed. Not done.

[Problem to be solved by the invention]

Since the conventional DMA device is configured as described above,
In data transfer corresponding to the size of the temporary register, it is always necessary to execute a read cycle and a write cycle in succession.

If the transferred data is large, the transfer source device or transfer destination device will be occupied more than necessary, leading to a reduction in the throughput of the entire system.

Furthermore, when transferring the same data to storage areas at multiple destination addresses, even though the source data is the same, it is necessary to execute a read bus cycle every time a temporary register size data is transferred, which reduces efficiency. Not on point.

Furthermore, conventional DMA devices cannot perform operations such as inverting transferred data or performing arithmetic processing with a certain value at the same time as DMA transfer.

The present invention was made to solve the above-mentioned problems, and it is possible to execute read cycles or write cycles continuously, and also to transfer the same data or the same block data.

It is an object of the present invention to provide a DMA device that can complete a read cycle of data or block data in one time, and can also perform inversion of data or arithmetic processing with a certain value at the same time as DMA transfer.

[Means to solve the problem]

The DMA device according to the present invention has a built-in temporary storage means for temporarily storing transfer source data from a peripheral device or a main memory device, and has a read operation for transferring the transfer source data to the temporary storage means, and a read operation for transferring the transfer source data to the temporary storage means. Performing a write operation to transfer data stored in the temporary storage means to the peripheral device or the main memory, and performing one or more consecutive read operations and one or more consecutive write operations. and a built-in control means for controlling continuous data transfer to one or more storage areas of the peripheral device or the main storage device, and further includes a control means for controlling continuous data transfer to one or more storage areas of the peripheral device or the main storage device, and further includes calculation data for performing calculations with the transfer source data. It has a built-in storage means for storing data, and a built-in control means for inverting the transfer source data or performing arithmetic or logical operations with the operation data stored in the storage means at the same time as data transfer.

[For production]

The temporary storage means in the present invention is controlled by the control means for controlling read and write operations to temporarily store transfer data so that read bus cycles can be carried out continuously and efficiently.

Further, the control means for performing inversion or arithmetic processing on the transfer source data inverts the transfer source data or performs arithmetic processing on previously prepared arithmetic data at the same time as the DMA transfer.

〔Example〕

FIG. 1 is an internal configuration diagram of an embodiment of the present invention. 1st
In the figure, (211) is the DMA@ control circuit, (212) is the transfer source address control circuit, (213) is the transfer destination address control circuit, (214) is the built-in memory circuit, (215) is the arithmetic processing circuit, and (216) is the transfer destination address control circuit. is an arithmetic data storage circuit, (21
7) is an internal address control circuit for reading, (218) is an internal address control circuit for writing, (6) is a data bus, (7) is an address bus, and (8) is a control bus. It is the same as that shown in FIG.

Prior to DMA transfer, the CPU (11) and DMA device (
2), an arbitration operation for the right to use the bus is performed. This operation is similar to conventional DMA devices. When the DMA device acquires the right to use the bus, it begins DMA operation.

The DMA operation of a DMA device that is an embodiment of the present invention will be described below. At the beginning of the DMA operation, the DMA device (2)
outputs the source address to the source device through the source address control circuit (212), and at the same time, the DMA control circuit (211) sends a data read signal to the source device through the control bus (8). At this time, when reading, the internal address control circuit (217) is connected to the internal storage device (214).
Outputs the storage address of the transfer source data to. As a result, the transfer source data is transferred to the built-in storage device (214) in the DMA device (2) (read cycle). If it is necessary to perform an operation on the transferred data at the same time as the transfer, the operation is performed in the arithmetic processing circuit (215). The arithmetic processing circuit (215) performs bit-by-bit inversion processing of the transfer source data, or performs bit-by-bit inversion processing of the transfer source data and the arithmetic data storage circuit (215).
216) is used to perform arithmetic processing with the arithmetic data stored in advance. The designation of this calculation process and the storage of calculation data in the calculation data storage device are performed using DMA.
Do this before starting the operation. Furthermore, if the transferred data is larger than the data bus size and cannot be completed in one read cycle, this read cycle is continued until all the source data is transferred. At this time, the DMA control circuit (211) sequentially specifies the transfer source data to be read in each read cycle by controlling the transfer source address control circuit (212), and sets the internal address of the storage location of the built-in memory circuit (214). At the time of reading, the internal address control circuit (217) is controlled to specify sequentially. When all the transfer source data is stored in the built-in memory circuit (214), D
The MA device (2) then controls the transfer destination address control circuit (21
At the same time as outputting the transfer destination address to the transfer destination device through the control bus (8), the DMA control circuit (211) sends a data write signal to the transfer destination device via the control bus (8). At this time, the write internal address control circuit (218) outputs the storage address of the data to be sent to the transfer destination device to the built-in storage device (214). As a result, the contents of the built-in memory circuit (214) are transferred to the transfer destination address control circuit (213).
) is transferred to the data storage location of the destination device specified by (write cycle). In addition, if the transferred data cannot be completed in a write cycle with a degree larger than the data bus size, this write cycle is
Continue until all the data stored in 4) has been transferred.

At this time, the DMA control circuit (211) sequentially specifies the address of the write location in the transfer destination device for each write cycle by controlling the transfer destination address control circuit (213), and stores it in the built-in storage circuit (214). The internal address of the storage location of the transferred source data is sequentially designated by controlling the internal address control circuit (218) during writing. The DMA operation ends when all data stored in the built-in storage circuit (214) is transferred to the destination device.

FIG. 5 shows the flow of eight DMA operations of this DMA device (2).

By the above operation, data transfer from the transfer source device and data transfer to the transfer destination device can be performed at once, and the time occupied by the transfer source device and the transfer destination device can be minimized. Furthermore, calculation processing can be performed simultaneously with the transfer.

Next, a DMA operation when the transfer source data are the same will be explained. FIG. 7 is a DMA operation flow when one piece of data in a transfer source device is transferred to n storage locations in a transfer destination device. It is assumed that the data size is the same as the data bus size, and one piece of data is transferred in one read cycle or write cycle. In this case, the read cycle is executed only once because there is only one piece of transfer destination data. After the read cycle is completed, the write cycle is repeated n times. At this time, the internal address that is applied to the built-in storage circuit (214) from the internal address control circuit (218) during writing is fixed, and the transfer destination address from the transfer destination address control circuit (213) is specified sequentially for each write cycle. be done. In conventional DMA devices, read cycles are performed n times, but with this operation, only one read cycle is required, so the read cycle time for the entire DMA transfer is n-
This will shorten the time required for one session.

Furthermore, an explanation will be given of an operation when source block data consisting of a plurality of pieces of data is transferred as a plurality of pieces of destination block data. FIG. 8 is a DMA 0 operation flow when transferring source block data consisting of n pieces of data to a plurality of destination blocks. After the DMA operation starts, the block data of the transfer source device is transferred to the built-in storage circuit (214) by executing n read cycles. After the read cycle is completed, the internal address control circuit (218) for writing uses the built-in memory circuit (214).
The start address of the block data stored in the transfer destination device is set, and the start address of the first block of the transfer destination device is set in the transfer destination address control circuit (213).
A write cycle for the first block is entered.

Perform a write cycle n times on the first block of the transfer destination device while sequentially changing the internal address of the write internal address control circuit (218) and the transfer destination address of the transfer destination address control circuit (213). by doing,
The transfer of the first block data of the transfer destination device is completed. Next, the write internal address control circuit (218
) The start address of the block data stored in the K built-in storage circuit (214) is set again, and the start address of the second block of the transfer destination device is set in the transfer destination address control circuit (213), A write cycle for the second block is performed. Similarly, the write cycle is repeated until the final block, and when the transfer of the final data of the final block is completed, the DMA operation ends. In conventional DMA devices, read cycles are performed n times for each transfer destination block, but with this operation, n read cycles are only required once for the transfer source block data, significantly reducing the overall DMA transfer time. is planned.

〔Effect of the invention〕

As described above, according to the present invention, since read cycles and write cycles can be performed at once, the time occupied by the transfer source device or the transfer destination device can be minimized, and the throughput of the entire system can be improved. effective.

Further, in the DMA transfer of the same data or block data, the read cycle can be executed with a minimum number as described above, so that the DMA transfer time can be shortened.

Furthermore, by providing an arithmetic processing device, it is possible to perform arithmetic processing on transferred data simultaneously with DMA transfer.

[Brief explanation of the drawing]

FIG. 1 is an internal configuration diagram of an embodiment of the present invention, and FIG.
The figure is a system configuration diagram using a DMA device, and FIG. In the figure (211) is DM
A control circuit, (212) is the transfer source address control circuit, (
213) is a transfer destination address control circuit, (214) is a built-in memory circuit, (215) is an arithmetic processing circuit, (216) is an arithmetic data storage circuit, (217) is an internal address control circuit for reading, and (218) is a writing circuit. (7) is an address bus, and (8) is a control bus. In Figure 2, (1) is the central information processing bag fl (CPU
), (2) are direct memory access devices (DMA devices)
, +31 is the main memory, (4) is the input device, (5) is the output device, (6) is the data bus, (7) is the address bus,
(8) is the control bus, and @lI is the main memory (2
) is the transfer source storage area, and 64 is the transfer destination storage area in the main storage device (2). In FIG. 3, (221) is a DMA control circuit, (222)
) is a transfer source address control circuit, (223) is a transfer destination address circuit, (224) is a temporary register, (6) is a data bus, (7) is an address bus, +81
It is a control bus. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. Direct memory access (controlling data transfer between a peripheral device and a main memory device, or data transfer between different storage areas within the main memory device, without going through a central information processing unit)
A DMA) control device includes a built-in temporary storage means for temporarily storing transfer source data from the peripheral device or the main storage device, and a read operation for transferring the transfer source data to the temporary storage means; Performing a write operation to transfer data stored in the temporary storage means to the peripheral device or the main memory, and performing one or more consecutive read operations and one or more consecutive write operations. A semiconductor integrated circuit comprising a control means for controlling continuous data transfer to one or more storage areas of the peripheral device or the main memory device. 2. In the scope of claim 1 above, the storage means for storing calculation data for performing calculations with the transfer source data is built-in, and at the same time as the data is transferred, the transfer source data is inverted or stored in the storage means. A semiconductor integrated circuit comprising a built-in control means for performing arithmetic or logical operations with the stored operation data.