JP2985496B2 - DMA transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA transfer system,
In particular, it relates to a DMA transfer method between a main memory and a plurality of peripheral devices.

[0002]

2. Description of the Related Art In a direct memory access transfer system (hereinafter, referred to as a DMA transfer system), a central processing system in which peripheral devices and the like are connected to a main bus.
Data can be directly transferred to and from the main memory without a unit (hereinafter, referred to as a CPU). In the conventional DMA transfer system, as shown in FIG.
7, a main memory 22, a plurality of peripheral devices 25 and 26,
Arbitration circuit 23 for arbitrating the right to use the main bus, peripheral device 2
A DMA controller 24 for controlling the DMA transfer between the main memory 22 and the main memory 22 and the CPU 21 are connected. To perform the DMA transfer between the peripheral devices 25 and 26 and the main memory 22, first, the microprocessor 28 in the peripheral devices 25 and 26 issues a request S14 to the local bus arbitration circuit 31 in the peripheral device. In response to the request S14, the arbitration circuit 31 sets the local bus 32
, The request S10 is issued to the main bus arbitration circuit 23. When the arbitration circuit 23 acquires the right to use the main bus 27, the arbitration circuit returns an acknowledge S11 to the arbitration circuit 31. The arbitration circuit 31 receives this and returns an acknowledgment S15 to the microprocessor 28. When the acknowledge S15 is returned, the microprocessor 28
The startup S12 is applied to the controller 24, and the internal memory 2 is stored in the register E connected to the DMA controller 24.
In addition to writing the address 9, the address of the main memory 22 is written into the register F, the data length is written into the register G, the gate 30 is opened, and the DMA transfer is started. As a result, the internal memory 29 is moved from the main memory 22
Is directly transferred to the memory. When the DMA transfer is completed, the requests S14 and S10 for the right to use the local bus 32 and the main bus 27 are released, the gate 30 is closed, and the buses 27 and 32 are released.

[0003]

SUMMARY OF THE INVENTION The above-described conventional DMA
In the transfer method, if the right to use the local bus 32 is not obtained even if the right to use the main bus 27 is obtained,
Since nothing can be performed while holding the number 2, the efficiency of the local bus 32 is low. Further, since the main bus 27 is held until the transfer of the data length written in the register G is completed, if the data length is long, even if the data is transferred from another peripheral device on the way, the previous data is not transferred. It is necessary to wait until the transfer is completed, during which the processing is stopped, and there is a problem that the processing efficiency is poor. Further, when the bus width of the main bus 27 and the bus width of the local bus 32 are different, one D bus
There is a problem that the amount of data that can be sent by MA transfer is limited to the bus width of the local bus 32 having a narrow bus width.

The present invention has been proposed to solve the problems of the prior art, and can improve the efficiency of a local bus at the time of DMA transfer between a peripheral device and a main bus. It is an object of the present invention to provide a DMA transfer system which enables parallel processing of peripheral devices of the above, and furthermore, the bus widths of the main bus and the local bus are different and each bus width can be fully utilized.

[0005]

In order to achieve this object, a DMA transfer system according to the present invention comprises: a main memory on a main bus; an arbitration circuit for arbitrating the right to use the main bus;
A plurality of peripheral devices for performing DMA transfer are connected to the main memory. The plurality of peripheral devices include a microprocessor for controlling the internal operation of the device, an internal memory for storing transfer data, and the main memory. Data storage means for temporarily storing data to be DMA-transferred; a first DMA controller for controlling DMA transfer between the internal memory and the data storage means; and a first DMA controller for controlling the DMA transfer between the main memory and the data storage means. Second to control DMA transfer
DMA controller is connected by a local bus and provided from the data storage means.
The DMA transfer to the in-memory is performed by the second DMA controller.
The arbitration circuit sends the data to the arbitration circuit every word of the transfer data.
By issuing a main bus request
A configuration for performing parallel processing of the plurality of peripheral devices.
is there.

[0006]

According to the present invention having the above construction, the main
DMA transfer between external memory and internal memory in peripheral devices
When performing, the DM between the internal memory and the data storage means is performed.
A transfer and DM between data storage means and main memory
A transfer can be performed separately from the
There is no need to obtain the right to use the local bus and local bus.
The efficiency of data transfer in Calvas can be increased. Ma
The right to use the main bus is set for each word of transfer data.
DMA transfer is performed while returning to the arbitration circuit.
And in, only one of the peripheral device I not dedicated have a main bus
Another peripheral device is requesting the main bus.
Transfer the right to use the main bus to that peripheral device.
it can. This allows parallel processing by multiple peripheral devices
It becomes possible.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific embodiment of the DMA transfer system according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the DMA transfer system. In this figure, a CPU 1, a main memory 2, a main bus arbitration circuit 3, and a plurality of peripheral devices 4 and 5 are connected to a main bus 6. These peripheral devices 4 and 5 have a similar internal configuration. The peripheral devices 4 and 5 have a local bus 1
3, a microprocessor 7 and an internal memory 8 are connected, and a DMA between the peripheral device and the main memory 2 is connected.
Flip-flop 9 serving as data storage means for temporarily storing transfer data; first DMA controller 1 controlling DMA transfer between internal memory 8 and flip-flop 9
1. DMA between flip-flop 9 and main memory 2
A second DMA controller 12 for controlling transfer and a local bus use right arbitration circuit 18 are connected by the local bus 12. Here, the flip-flop 9 is connected to the main bus 2 via the gate 10.

[0008] Next, an operation procedure for performing the DMA transfer between the peripheral device 4, 5 and the main memory 2 in the DMA transfer method thus constructed. First, to perform DMA transfer from the peripheral device to the main memory 2, the microprocessor 7 activates the DMA controller 11 to start S1, writes an internal memory address to the register A, and writes a data length to the register B. Subsequently, the DMA controller 11 issues a request S2 to the local bus use right arbitration circuit 18, and when the right to use the bus 13 is obtained, the arbitration circuit 18 returns an acknowledgment S3 to the DMA controller 11 and sends the request from the internal memory 8 to the flip-flop 9. Data S4 is transferred. At this time, the microprocessor 7 transfers the entire data length of the data to be transmitted to the main memory 2 to the flip-flop 9. Subsequently, the microprocessor 7 starts the DMA controller 12, writes the main memory address in the register C, and writes the data length in the register D. Then DM
The A controller 12 issues a request S5 to the main bus use right arbitration circuit 3, and when the right to use the bus 6 is obtained, the arbitration circuit 3 returns an acknowledge S6 to the DMA controller 12. As a result, the gate 10 opens, and the data S7 is transferred from the flip-flop 9 to the main memory 2.

In the transfer between the flip-flop 9 and the main memory 2, when the transfer of one word is completed, the request for the right to use the main bus is once released, and the bus 6 is released. If data to be transferred remains, a request for the bus 6 is issued again, and this is repeated until there is no more data. When the DMA transfer is being performed on the main bus 6, the microprocessor 7 and the local bus 13 can execute their own processing.

[0010] On the other hand, a peripheral device from the main memory 2 4,5
When performing a DMA transfer, the procedure described above is reversed.
First, data is transferred from the main memory 2 to the flip-flop 9, and then data is transferred from the flip-flop 9 to the internal memory 8.

When the main bus 6 and the local bus 13 have different bus widths, for example, when the main bus 6 has 32 bits and the local bus 13 has 16 bits,
By providing two flip-flops 9, the internal memory 8
16 bits between the flip-flops 1 and 2 are alternately transferred between the main memory 2 and the flip-flops, and 32-bit data is transferred between the main memory 2 and the flip-flops to the flip-flops 1 and 2 at a time. can do.

The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist.

[0013]

As described above, according to the present invention, when performing DMA transfer between the main memory and the internal memory in the peripheral device, the data storage means provided between the local bus and the main bus is provided. Since data can be transferred via the local bus, it is not necessary to simultaneously acquire the right to use the local bus and the main bus, and the efficiency of the local bus can be improved. Also, the right to use the main bus is released each time one word transfer is completed, so that the right to use can be transferred if another peripheral device issues a request.
There is an advantage that a plurality of peripheral devices can be processed in parallel. Further, when the bus width of the main bus is different from that of the local bus, there is an advantage that transfer utilizing the bus width of each bus can be performed by providing a plurality of flip-flops serving as temporary data storage means. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a DMA transfer system according to the present invention.

FIG. 2 is a block diagram showing a conventional DMA transfer system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Main memory 3 Main bus arbitration circuit 4, 5 Peripheral device 6 Main bus 7 Microprocessor 8 Internal memory 9 Flip-flop 10 Gate 11 First DMA controller 12 Second DMA controller 13 Local bus

Claims (1)

(57) [Claims] And 1. A main to the main bus memory, an arbitration circuit that arbitrates the right to use the main bus, the main memory and performs a DMA transfer multiple peripheral devices are connected, within the plurality of peripheral devices, apparatus , An internal memory in which transfer data is stored, data storage means for temporarily storing data to be DMA-transferred to the main memory, and a data storage means for storing data between the internal memory and the data storage means. First D for controlling DMA transfer
An MA controller and a second DMA controller for controlling DMA transfer between the main memory and the data storage means are provided by being connected by a local bus, and are provided from the data storage means to the main memory.
Is transferred by the second DMA controller.
Data for each word of the
By issuing a request for
A DMA transfer system that performs parallel processing of peripheral devices .