JPH04116751A - Data transfer system - Google Patents

Abstract

PURPOSE:To realize transfer in an efficient cycle by permitting a direct memory access (DMA) cycle to hold CPU by memory access time. CONSTITUTION:When a DMA device (DMAC) 4 transfers data, a holding request signal (HRQ signal C) which requests the use of a bus is not asserted while a local data bus 6 connected to I/O 5 is accessed and it is transferred to a transceiver 3 having a data holding function through an arbiter 6. Then, the HRQ signal C is asserted as against CPU 1, the use right of the bus is obtained and it transferred to a memory 2. Thus, time when CPU holds can be shortened. Thus, transfer is executed at the efficient cycle.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention is directed to direct memory access (hereinafter referred to as DM), which is frequently used for data transfer on floppy disks or hard disks in computers, word processors, etc.
(referred to as A) relates to a device capable of transfer.

(Prior art) Generally, in devices such as computers and word processors, it is possible to transfer data from floppy disks and hard disks at high speed between ■10 and memory without going through the central processing unit (hereinafter referred to as CPU). MA transfer has been widely used. DMA here
A general explanation of the transfer will be provided. When transferring data from the floppy disk controller to memory, CPtJ
When data is transferred via the I10 read cycle, the data is once taken into the register of the CPU, and then the data in the register is transferred to the memory in the memory write cycle.

That is, data is transferred in two cycles. On the other hand, in DMA transfer, a specific select signal (D A CK signal) and I10 read signal (■○R
D signal), an address and a memory write signal (MEMW times signal) are output to the memory, and data is transferred in one cycle.

(Problem to be Solved by the Invention) However, DMA transfer, which is characterized by high-speed data transfer, does not have a faster processing cycle (1 cycle 500 ns) compared to recent CPU speeds (1 cycle 100 ns diameter). For this reason, two-cycle transfer using the CPU can be faster than one-cycle transfer using DMA transfer.

However, the Ilo access time is slower than the memory access time, and when these transfers are performed by the CPU, the CPU is generally devoted to data transfer, making it impossible to build an efficient system, resulting in slow MA transfer. Currently, it is still in use. In addition to these methods of increasing the DMA transfer speed, a method of shortening the time that the DMA device (DMAC) occupies the main data bus is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer method that can shorten the time that a DMAC occupies a main data bus.

(Means for Solving the Problems) In order to achieve the above-mentioned problems, the present invention provides data retention between a local data bus to which ■/○ capable of DMA transfer are connected and a main data bus to which memory is connected. Transceiver with functions and engineering/engineering of both CPU and DMAC
It is equipped with an arbitration circuit (arbiter) that arbitrates access to ○.

(Function) Therefore, according to the present invention, the hold request signal (
The HRQ signal (hereinafter referred to as HRQ signal) is not asserted during access to the local data bus to which Ilo is connected, and is transferred to a transceiver having a data retention function via an arbiter.
Thereafter, the HRQ signal is asserted to the CPU to obtain the right to use the bus and transfer to the memory. This makes it possible to shorten the time the CPU holds.

(Embodiment) FIG. 1 shows the configuration of a data transfer system in an embodiment of the present invention. In Figure 1, 1 is the CPU, 2
is the memory connected via main data bus a,
3 is a transceiver that is located between the main data bus a and the local data bus 5 and has the function of holding data; 4 is a DMACl3 is a transceiver capable of DMA transfer; 6 is a transceiver capable of DMA transfer;
This is an arbiter that mediates access between PUI and DMAC4.

Also, C is the HRQ signal output from DMAC4, and d is H
Response signal (HLDA) to RQ signal, e is CPUI
A request signal for accessing Ilo (Engineering○A)
C3), f is a request signal (DMAIO) for DMAC 4 to access work/○, g is a transceiver control and I10 permission signal arbitrated by arbiter 6, and h is a data request signal (D REQ), i is a response signal (DACK) of the data request signal.

FIG. 2 shows a timing chart of DMA transfer (transfer from Ilo to memory) in one embodiment of the present invention, and FIG. 3 shows a timing chart of conventional DMA transfer (transfer from Ilo to memory). It shows.

Next, a procedure for transferring data from Ilo to memory in the above embodiment will be explained.

When the signal DREQ requesting data transfer from ■/○ is asserted, the DMAC 4 sends the arbiter 6 to ■/○.
Outputs the DMA signal f, which is an access request signal. After arbitration in arbiter 6, DMAC4 receives DACK
It outputs the signal i signal - and causes the transceiver 3 to hold the data from l105. After this, DMAC4 uses CP
The HRQ signal is input to U1, and the data held in the transceiver 3 is transferred to the memory 2 via the main data bus a on the HLDA signal d.

Next, when transferring data from memory 2 to workpiece 105,
When the DREQ signal is output from l105, DMAC4
The signal amount of the HRQ signal is asserted.

When the HLDA signal d is input, data is stored in the transceiver 3 from the memory 2. After that, the HRQ signal amount is gated and the main data bus a is returned to the CPU1 for DMA
When the I○ signal f is asserted and a permission signal is received by the arbiter 6, the data in the transceiver 3 is sent to the transceiver 3 by the DACK signal 1 and the write signal.

Comparing the timing charts for data transfer from I/○ to memory in this embodiment and the conventional example shown in Figures 2 and 3, the time during which the CPU cannot use the main data bus is longer in this embodiment than in the conventional example. It can be seen that the time period has been significantly shortened.

(Effects of the Invention) As is clear from the above embodiments, the present invention is an efficient cycle because the CPU only needs to be held during the memory access time in the DMA cycle, and the time during which the DMAC occupies the main data bus is shortened. This has the effect that transfer can be performed.

[Brief explanation of the drawing]

Figure 1 is a system configuration diagram of a data transfer method in an embodiment of the present invention, and Figure 2 is a DM system diagram in an embodiment of the present invention.
Timing chart of A transfer. FIG. 3 is a timing chart of DMA transfer in a conventional example. 1...CPU, 2...Memory, 3.
・Transceiver, 4 ・DMAC, 5 ・Engineering/○, 6 ・Arbiter, a ・Main data bus, b ・Local data bus, c −・
HRQ signal, d・-HLDA signal, e...
l0AC3 signal, f...0MA10 signal, g
... Transceiver control and I10 enable signal, h ... DREQ signal, 1 ... DACK signal. Patent applicant Matsushita Electric Industrial Co., Ltd.

Claims (1)

[Claims] A main memory element (memory) connected to a central processing unit (CPU) via a main data bus, and a direct memory access device (DMAC) capable of high-speed transfer between the memory and I/O without going through the CPU. and a local data bus to which the I/O capable of direct memory access transfer is connected, and the CPU is accessing the I/O;
Alternatively, the data transfer method includes an arbitration circuit that determines whether the DMAC is accessing the I/O and performs arbitration, and a transceiver that can hold data between the local data bus and the main data bus.