JPH04280344A - Memory device - Google Patents

Abstract

PURPOSE:To provide a line buffer between a main memory and a global cache memory and to avoid contention between bus masters to eliminate bottle neck in a bus. CONSTITUTION:The line buffer 34 is provided between the main memory 36 and the global cache memory 32 of a memory device 31. The bus master of CPU 12 which is permitted to use a system bus 11 accesses to the memory device 31 from a bus arbiter 20. When the cache memory 32 mishits, a block is transferred to the cache memory 32 from the main memory 36 through the line buffer 34. At the time of transferring data from the main memory 36 to the line buffer 34, a bus temporary release answer 39 is transmitted from a control circuit 37 to the bus arbiter 20. The bus master accessed to the memory device 31 is caused to release the system bus 11.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device connected to a system bus in an information processing system in which a plurality of bus masters are connected to the system bus.

0002

[Prior Art] Conventionally, for example, Japanese Patent Application Laid-Open No. 1149-1989
As shown in Publication No. 53, the CPU is connected to the system bus.
and direct memory access (hereinafter referred to as DMA).
There is an information processing system in which a plurality of bus masters such as a control device and a memory device are connected and controlled by a bus arbiter so that only one of these bus masters obtains usage rights at the same time.

0003

[Problem to be Solved by the Invention] In such an information processing system, when a bus master accesses a memory device, when this bus master presents a request to use the system bus to the bus arbiter, another bus master has already acquired the bus. Because the bus master is currently in use, the bus master is forced to wait until the bus becomes free, which often results in a so-called bus neck condition in which the bus master is unable to demonstrate its original performance.

[0004] In order to avoid this bus neck, for example, the following means can be considered. (1) Speed up the system bus. (2) Multiplex the system bus. (3) Provide local cache memory for each bus master. Of these, methods (1) and (2) improve the transfer capacity of the system bus, but they inevitably require a unique bus architecture, which is impossible if a standard bus is used. Furthermore, the method (3) not only increases the amount of system material, but also requires complex control to ensure data consistency between each local cache memory and the main memory. Furthermore, if the hit rate of the cache memory is not high enough, there is a risk that block transfers that occur on the system bus in the event of a miss may significantly impede other bus masters from using the bus. In addition,
JP-A-57-103178 discloses a technique for improving the hit rate of cache memory.

[0005] Since the above-mentioned method (3) also has the above-mentioned problem, as a means to avoid the bus neck, Japanese Patent Laid-Open No. 1-22
As shown in Japanese Patent No. 9345, it is conceivable to provide a cache memory on the memory device side. However, in this case, if the cache memory misses when the bus master accesses the memory device, a block transfer is performed from the main memory to the cache memory, but during this block transfer, the bus master accessing the memory device actually Since the bus continues to be occupied even though the bus is not in use, the bus neck still remains unresolved.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory device that can eliminate bus necks by avoiding conflicts between bus masters as much as possible.

[0007]

A memory device according to claim 1 is a memory device connected to a system bus to which a plurality of bus masters are connected, and at the same time, only one of these bus masters permitted by a bus arbiter uses the system bus. A main memory, a cache memory provided between the main memory and the system bus and having a shorter access time than the main memory, and a cache memory provided between the main memory and the cache memory that provides access from the bus master to the memory device. When writing, the data from the cache memory is held all at once and transferred to the main memory in sequence, and when reading from the memory device to the bus master, the data read from the main memory is held sequentially so that all data of one line length is read out. The system also includes a line buffer that transfers data in batches to the cache memory, and control means that sends an instruction to the bus arbiter to release the system bus when transferring data from the main memory to the line buffer.

In this memory device, if there is a miss in the cache memory when reading from the memory device to the bus master, a block is transferred from the main memory to the cache memory, but at this time, the data read from the main memory is transferred to the line buffer. After all data of one line length that is held sequentially is read out, it is transferred all at once from this line buffer to the cache memory. When transferring data from the main memory to the line buffer, the control device sends an instruction to the bus arbiter to release the system bus, thereby releasing the system bus.

[0009] The memory device according to the invention according to claim 2 is characterized in that the main memory according to the invention according to claim 1 is dynamically R
It is configured using AM, and the cache memory is configured using high-speed static RAM.

0010

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 to 3 relate to one embodiment of the present invention.

FIG. 1 is a block diagram showing the general configuration of an information processing system including a memory device according to an embodiment of the present invention. This information processing system includes a system bus 11 and a C bus master connected to the system bus 11.
It includes a PU 12, a DMA control device (1) 21, and a DMA control device (2) 22. These CPU12, DM
A control device (1) 21 and DMA control device (2) 22
is a bus arbiter 20 that grants permission to use the system bus 11 to only one of these bus masters at the same time.
It is connected to the. Note that the CPU 12 is connected to the system bus 11 via the CPU cache memory 13, and the CPU 12 and the CPU cache memory 13 are connected to the system bus 11 via the CPU cache memory 13.
They are connected via the U bus 14. Further, the DMA control device (1) 21 is connected to and controls a high-speed communication line 23 such as ISDN, and the DMA control device (2) 22 is connected to and controls the fixed disk device 24. Further, the memory device 31 of this embodiment is connected to the system bus 11. Further, a low-speed input device 16, a display device 17, a printing device 18, etc. are connected to the system bus 11 via a low-speed input/output control device 15.

The memory device 31 includes a global cache memory 32 directly connected to the system bus 11, a line buffer 34 connected to this cache memory 32 via a cache bus 33, and a line buffer 34 connected to this cache memory 32 via a buffer bus 35. It includes a main memory 36 connected to the buffer 34, and a control circuit 37 that controls the global cache memory 32, line buffer 34, and main memory 36. The main memory 36 is configured using dynamic RAM (hereinafter referred to as DRAM),
Global cache memory 32 is this main memory 3
Faster static RAM with faster access time than 6
(hereinafter referred to as SRAM). Further, the control circuit 37 is connected to the bus arbiter 20.

FIG. 2 is a block diagram showing the detailed structure of the memory device 31. As shown in this figure, the cache memory 32 includes a data memory 41, a tag memory 42,
It has a selector 43 provided between the data memory 41 and the system bus 11. Here, system bus 1
The width of 1 is 8 bits. The line length of the data memory 41 is 4 bytes, and one of the four areas of 8-bit data width of each line is selectively connected to the system bus 11 by the selector 43. The tag memory 42 also stores an address (Addr) on the main memory 36 of the data stored in the data memory 41.
ess: Indicated as ADR in FIG. 2. ) and whether or not the data is valid (Valid: denoted as V in FIG. 2) are stored.

The line buffer 34 is connected to the data memory 41
Each 8-bit wide area of the line buffer 34 is connected to each 8-bit wide area of the data memory 41, respectively. Further, the main memory 36 includes a DRAM 46 and this DR.
It has a selector 47 provided between the AM 46 and the line buffer 34. And line buffer 34
One of the 8-bit wide areas is selectively connected to the DRAM 23 by a selector 47. Here, both selectors 43 and 47 are bidirectional.

Next, the operation of this embodiment will be explained with reference to FIGS. 3 and 4. FIG. 3 is a time chart for explaining the operation of this embodiment, and FIG. 4 is a time chart for explaining the conventional operation.

In the memory device 31 of this embodiment, when data is written from the bus master to the memory device 31, the data from the system bus 11 is written to the cache memory 32 and also to the main memory 36. In this case, the line data from the data memory 41 of the cache memory 32 is collectively held by the line buffer 34 and sequentially transferred to the DRAM 46 of the main memory 36 via the selector 47.

Furthermore, when reading data from the memory device 31 to the bus master, the bus master first accesses the tag memory 42 of the cache memory 32, and if there is a hit, the data memory 41 of the cache memory 32 is accessed.
Desired data is read from. On the other hand, in the event of a miss, a block is transferred from the main memory 36 to the cache memory 32. In this case, data read from the DRAM 46 of the main memory 36 is sequentially stored in the line buffer 34 via the selector 47, and after all data of one line length is stored in the line buffer 34, the line buffer 34 The data is transferred all at once to the data memory 41 of the cache memory 32. As shown in FIG. 1, a cache memory 32, a line buffer 3
4 and the main memory 36 are controlled by a control circuit 37.
When data is transferred from the DRAM 46 of No. 6 to the line buffer 34, the bus arbiter 20
A bus temporary release response 39 is sent, which is an instruction to release the bus. This frees up the system bus 11.

A specific example of the operation of this embodiment will now be described with reference to FIG. In this example, as shown in (b), the CPU 12 first issues a bus use request to the bus arbiter 20 at point A1. This CPU 12 receives permission to use the bus from the bus arbiter 20 at point B1 and acquires the right to use the bus. Thereafter, the CPU 12 accesses the memory device 31 via the system bus 11, and the system bus 11 becomes busy as shown in (a). As shown in (c), when the CPU 12 accesses the tag memory 42 of the global cache memory 32 at point C1 and it is found that the cache memory 32 is a miss, the control circuit 37 causes the bus arbiter 20 to temporarily access the bus at point G1. A release response 39 is sent. The bus arbiter 20 receives this bus temporary release response 39, and the bus arbiter 20
2 to suspend use of the system bus 11, and the system bus 11 is released.

Furthermore, as shown in (e), the control circuit 37
points D1 at the same time as point G1, which issues a bus temporary release response 39.
At this point, the DRAM 46 of the main memory 36 is activated, and the data of the block containing the data requested by the CPU 12 is read out from the DRAM 46 using a first page mode or the like, and is sequentially stored in the line buffer 34 via the selector 47. , 1 in this line buffer 34
When all line length data has been stored, as shown in (d), the line buffer 34 is transferred to the cache memory 3.
2 data memory 41, and this data transfer is completed at point E1.

Up to this point, the cache memory 32 is in an idle state and is therefore able to accept access requests from other bus masters. In the example shown in Figure 3, (
As shown in f), the DMA control device issues a bus usage request at point A2, acquires the right to use the bus at point B2 after the CPU 12 releases the system bus 11, and (
At point C2 shown in c), the tag memory 42 of the cache memory 32 is accessed. Then, the cache memory 32 is hit, the transfer of data from the cache memory 32 to the DMA control device is completed at point E2, and the DMA control device transfers the
At point 2, the use of the system bus 11 is completed and the system bus 11 is released.

[0021] The CP that first accessed the memory device 31
U12 issues a request to use the bus several times until the desired data is transferred to the cache memory 32 (point A3).
, acquires the right to use the bus (point B3) and accesses the cache memory 32 of the memory device 31 (point C3), but
All receive a temporary bus release response (point G3) and release the bus again.

In the example shown in FIG. 3, the cache memory 32
After the desired data has been transferred to A5, the CPU 12
Before issuing a bus use request at
A bus use request is issued at point B4, the right to use the bus is acquired at point B4, and cache memory 3 is issued at point C4.
2 and accesses cache memory 3 at point E4.
The data transfer from 2 to the DMA control device is completed, and the DM
The A controller has finished using the bus at point F4 and has released it.

After the desired data has been transferred to the cache memory 32, the CP issues a bus use request at point A5.
U12 won the bus right at point B5 and moved to point C5.
At this point, the tag memory 42 of the cache memory 32 is accessed, this time a hit occurs, and the desired data is passed from the data memory 41 to the CPU 12 via the system bus 11. Then, at point E5, the data transfer from the cache memory 32 to the CPU 12 is completed, and the CPU
12 completes use of the bus at point F5 and releases it.

Here, for comparison with this embodiment, FIG.
The operation of a conventional memory device without a line buffer 34 will be explained using FIG. In this memory device, as shown in (b), the CPU that issued the bus use request at point A11:
The right to use the bus is acquired at point B11, and the global cache memory is accessed at point C11, as shown in (c). When it turns out that the cache memory is mishit, as shown in (d), at point D11,
The DRAM of the main memory is activated, and data in blocks including data requested by the CPU is sequentially transferred to the cache memory, and this data transfer is completed at point E11, as shown in (b). Thereafter, desired data is passed from the cache memory to the CPU via the system bus. Then, at point F11, the CP is transferred from the cache memory.
The transfer of data to U is complete and the CPU has finished using the bus and releases it. As shown in (e), the DMA control device that issued the bus use request at point A12 acquires the right to use the bus at point B12 after the bus is released at point F11,
At point F12, use of the bus is completed and it is released. In this way, in conventional memory devices, when a cache memory mishit occurs, the system bus is always busy from point B11 to point F11, including the block transfer period, as shown in (a), and a bus neck occurs. Easy to do.

On the other hand, in this embodiment, the line length of the data memory 41 of the cache memory 32 is taken as the capacity for one block transfer, and the line buffer 34 with the same storage capacity as this line length is used as the data memory 41 of the cache memory 32.
1 and the DRAM 46 of the main memory 36, the block transfer that occurs when the cache memory 32 misses is not performed directly between the DRAM 46 and the data memory 41, but is divided via the intermediate line buffer 34. Is going. Furthermore, multiple times between the DRAM 46 and the line buffer 34 (=line length [byte]/DRAM
During data transfer with a data width of 46 bytes, the bus master requesting access is temporarily disconnected from the system bus 11.
It is controlled to separate it from the Therefore, during that time, system bus 11 and cache memory 32 are freed, allowing other bus masters to interact with other hit address entries in cache memory 32. As described above, according to this embodiment, from the perspective of other bus masters, not only the system bus 11 but also the cache memory 32 have a high rate of being in an idle state, and bus necks can be effectively avoided. Moreover, the bus neck in the system can be eliminated, regardless of the problems caused by conventional improvement measures.

Furthermore, since the capacity of the line buffer in the present invention is approximately 8 bytes to 128 bytes, ASI
It is easy to incorporate it into a C, etc., and if it is incorporated into an ASIC such as a control circuit for a DRAM or cache memory, the increase in the amount of hardware due to the provision of a line buffer can be almost ignored.

Note that the present invention is not limited to the above embodiments,
For example, the bus masters on the system bus are the CPU and DMA.
The CPU is not limited to combination with a control device, and the CPU may not have a local cache memory.

In the embodiment, the width of the system bus 11 is 8 bits, the data memory 41 and the line buffer 3 are
The line length of 4 is 4 bytes, and the data width of DRAM46 is 8.
However, the present invention is not limited to these conditions,
Between the data memory 41 and the system bus 11 and between the line buffer 34 and the DRAM 46, a bidirectional selector 43,
Since the data width is matched by 47, any data width is possible.

Furthermore, the bus arbiter is not limited to a centralized type as shown in the embodiment, but may be a distributed type provided in each bus master.

[0030]

As described above, according to the present invention, a line buffer is provided between the main memory and cache memory of a memory device, and block transfer that occurs when a cache memory miss is performed via the line buffer.
Since the system bus is released when data is transferred from the main memory to the line buffer, conflicts between bus masters can be avoided as much as possible and bus necks can be eliminated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of an information processing system including a memory device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a memory device according to an embodiment of the present invention.

FIG. 3 is a time chart for explaining the operation of a memory device according to an embodiment of the present invention.

FIG. 4 is a time chart for explaining the operation of a conventional memory device.

[Explanation of symbols]

11 System bus 12 CPU 20 Bus arbiter 21, 22 DMA control device 31 Memory device 32 Global cache memory 34 Line buffer 36 Main memory 37 Control circuit

Claims (2)

[Claims] 1. A memory device connected to a system bus to which a plurality of bus masters are connected, and at the same time, only one of these bus masters permitted by a bus arbiter is used, the memory device comprising a main memory, the main memory and the a cache memory provided between the system bus and having a shorter access time than the main memory; and a cache memory provided between the main memory and the cache memory, which reads data from the cache memory when the bus master writes to the memory device. is held all at once and sequentially transferred to the main memory, and when reading from the memory device to the bus master, the read data from the main memory is held sequentially, and after all data of one line length has been read,
The present invention is characterized by comprising a line buffer that transfers data in batches to a cache memory, and a control means that sends an instruction to the bus arbiter to release the system bus when transferring data from the main memory to the line buffer. memory device. 2. A memory device connected to a system bus to which a plurality of bus masters are connected and at the same time only one of these bus masters permitted by a bus arbiter is used, the main memory device being configured using a dynamic RAM. a cache memory provided between the main memory and the system bus and configured using a high-speed static RAM; and a cache memory provided between the main memory and the cache memory and configured to provide communication from the bus master to the memory device. When writing, the data from the cache memory is held all at once and transferred to the main memory in sequence, and when reading from the memory device to the bus master, the data read from the main memory is held sequentially so that all data of one line length is read out. and a control means for sending an instruction to the bus arbiter to release the system bus when data is transferred from the main memory to the line buffer. A memory device characterized by: