JPH01142962A - Data transfer control system - Google Patents

Abstract

PURPOSE:To simultaneously attain data transfer between peripheral control parts and a CPU and a memory and to improve a system throughput by executing the data transfer between the peripheral control parts through a data bus in the peripheral control parts. CONSTITUTION:A bus assigning control part 201 of a bus control part 105 requests an access request for a data bus 106 from respective modules of a CPU 101, a main memory 102 and peripheral control parts A103 and B104 and assigns the use right of the data bus 106 for a module with a high priority. A bus SW control part 202 instructs the cutting/connecting of the data bus 106 for a bus SW 203 based on the request from the CPU 101 and peripheral control parts A103 and B104. The bus SW 203 executes the logical cutting and connecting of the data bus 106 between a CPU and the main memory and the peripheral control parts. At the time of cutting the bus 106, the simultaneous data transfer between the CPU and the memory, and peripheral control devices can be executed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data transfer control method for an information processing device,
Especially the central processing bag [(CPU), main memory.

The present invention relates to a data transfer control method in an information processing device in which peripheral control units have the same bus configuration.

[Conventional technology]

Conventionally, in an information processing device in which a CPU, main memory, and a peripheral control unit that controls peripheral devices are connected to the same bus, data transfer associated with main memory access of the C:PU and input/output operations with peripheral devices is as follows. It was done like this. In other words, data transfers associated with reading data from the main memory to the CPU and storing data from the CPU to the main memory are performed via the bus between the CPU and the main memory, and from one peripheral device to the main memory or vice versa. Data input/output is performed between the peripheral device and the main memory via the peripheral control unit and bus.

Furthermore, data transfer between peripheral devices involves first storing data from one peripheral device in the main memory via the peripheral control unit and bus, and then from the main memory via the bus and peripheral control unit. and transfer it to the other peripheral device.

[Problem that the invention seeks to solve]

In the above conventional technology, even data transfer between peripheral devices always goes through the main memory, so when the traffic of input/output operations increases, the usage rate of the main memory increases, and the main memory access of the CPU is There was a problem in that the waiting time ratio increased, leading to a decrease in system throughput. Additionally, data transfers associated with CPU main memory accesses and data transfers associated with input/output operations between the main memory of one peripheral device use the same bus, so when the traffic of input/output operations increases, the bus usage rate increases. However, there is a problem in that the proportion of main memory accesses of the CPU being waited for due to input/output operations increases, which also causes a decrease in system throughput.

Data transfer between the peripheral device and main memory is essential when a program on the CPU refers to or changes data on a peripheral device, or when a program on the CPU-U stores modified or newly created data in the peripheral device. However, if it is desired to output data input from a peripheral device to another peripheral device without any processing, there is no need to go through the main memory. For example, when data is input from an image reader and stored on a disk, or when image data on a disk is output to a fax machine, passing through the main memory becomes a system overhead. Even when data is transferred from a peripheral device that does not need to go through the main memory, conventional methods always go through the main memory, so when transferring large amounts of data such as image data, the usage rate of the main memory increases. The frequency of access conflicts between the CPU and the peripheral control unit in the main memory increases, resulting in a significant reduction in system throughput.

As a method of reducing access contention in main memory, there is a method of dividing main memory into a plurality of banks that can operate independently (memory interleaving), but this increases the amount of hardware and becomes expensive. There is a problem that main memory control becomes complicated. Further, as a method of reducing bus contention, a method of providing a plurality of buses can be considered, but this increases the amount of hardware for bus control in each module and becomes expensive.

There is a problem that inhibits the advantages of the bus configuration.

An object of the present invention is to provide a data transfer control method that makes it possible to reduce main memory access traffic and improve system throughput in an information processing device in which a CPU, main memory, and peripheral control unit are connected to the same bus. It is in.

[Means and effects for solving the problems] The present invention is based on C
Means is provided for controlling disconnection and connection of a bus between a first group consisting of a PU and main memory and a second group consisting of a plurality of peripheral control units.

By disconnecting the bus when transferring data between m peripheral devices, data can be transferred directly between the peripheral control units without going through the main memory, and at the same time data transfer between the CPU and main memory can be executed. Aim to reduce access traffic and improve system throughput. In addition, the bus connection enables data transfer between the peripheral control unit and the main memory, and it also handles cases where peripheral device data is referenced and updated by the CPU, and cases where the CPU outputs changed or newly created data to the peripheral device. It can be so.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an overall configuration diagram of an embodiment of an information processing apparatus to which the method of the present invention is applied. In FIG. 1, a CPU l01, a main memory 102, a peripheral control unit AlO3, and a peripheral control unit B1
04 and below are connected to each other by a data bus 106, and a plurality of peripheral devices 107 are connected below the 1 peripheral control unit AlO3 and the peripheral control unit B104, respectively. Data transfer between each module is performed via the data bus 106,
Control such as allocation of the right to use the data bus 106 is performed by the bus control unit 105.

FIG. 2 shows the detailed configuration of the bus control section 1051, peripheral control section AlO3, and peripheral control section B104. The bus control unit 105 includes a bus allocation control unit 201, a bus switch (bus SW) control unit 202, and a bus 5W203. The peripheral control unit 103 includes an interface control unit A204, a data transfer control unit A205. The structure of the 0 peripheral control section B104, which is composed of the data buffer A206, is also similar. Control information is exchanged between each module via a control line 210.

The bus allocation control unit 201 of the bus control unit 105
01. Upon receiving an access request to the data bus 106 from each module of the main memory 102, peripheral control unit A 103, and peripheral control unit B 104, the data bus 106 is sent to the module with the highest priority according to the priority of each module.
Assign usage rights. The bus allocation control unit 202
101, based on requests from peripheral control unit AlO3 and peripheral control unit B104, data bus 1 is sent to bus 5W203.
06 disconnection/connection instructions. Bus 5W203 is C
PUl01. Group of main memory 102 and peripheral control unit A
The data bus 106 is logically disconnected/connected between the IO3 and the peripheral control unit B104 group. data bus 10
When the bus 6 is in the disconnected state, the data bus 106 can operate as if two sets of independent buses existed. That is, data transfer operations between the CPU 10I and the main memory 102 and between the peripheral control unit AlO3 and the peripheral control unit 8104 can be performed simultaneously.

The peripheral control unit AlO3, the interface control unit A204 of the peripheral control unit B104, and the interface control unit B207 receive input/output instructions from the CPU101 and control the main memory 1.
Data transfer control unit A205.02 reads and decodes input/output control information from A205. Data transfer control unit 8
208 is activated. In addition, the end of input/output operation is
1. Report to Ol. Data transfer control unit A205. The data transfer control unit B2O3 is the interface control unit A20.
4. Based on the activation from the interface control unit B207, the peripheral devices 107 and the main memory 10 under the inner peripheral control unit
2 or between the peripheral device 107 under the inner peripheral control unit and other peripheral control units. Data buffer A206. The data buffer B209 is a buffer for temporarily storing data read from the peripheral device 107 or data written to the peripheral device 107.

FIG. 3 shows the operational flow between each module when performing input/output operations.

When the information processing device is powered on, the CPU l01, main memory 102, peripheral control unit AlO3, peripheral control unit B10
4. All modules of the bus control unit 105 are initialized (301). At the time of this initial setting, the bus 5W203 is set so that the data bus 106 is connected (3
02). Thereafter, execution of the instruction is started in CPUl0I (303).

When an input/output operation is required, a memory write command is issued prior to the input/output command, and the CPU 101 writes input/output control information to the main memory 102 via the data bus 106 (304). Peripheral control unit Al
When an input/output command to O3 is issued, CPUl01
Instructs the peripheral control unit AlO3 to start the input/output operation via the control line 210 (305).
Based on this, the interface control unit A204 in the internal peripheral controller A204 reads input/output control information from the main memory 102 via the data bus 106 (306), and the input/output operation request is transmitted between the internal peripheral control unit AlO3 and the other peripheral control unit B104. data transfer between the main memory 102 and the inner peripheral control unit Al.
It is determined whether the data transfer is during O3 (307).

In the case of data transfer between the main memory 102 and the inner peripheral control unit AlO3, based on the instruction from the interface control unit A204, the data transfer control unit A205 starts the specified peripheral device 107 and transfers one peripheral device [107 and the main memory 102 (308). That is, the manual data from the peripheral device 107 is transferred to the data buffer A206.
, data bus 106 to the main memory 102, and read data from the main memory 102 via the data bus 106. Peripheral bag FV via data buffer A206
It is output to 1107. When the data transfer operation is finished,
The data transfer control unit A205 writes the result of the input/output operation (normal termination/abnormal termination, information on the cause of the abnormality in the case of abnormal termination) in the main memory 102 (309). Thereafter, the interface control unit A204 issues an interrupt to CPUl0I to end the input/output operation.

If the input/output operation request is data transfer between the inner peripheral control unit AlO3 and other peripheral control unit B104, the inner peripheral control unit Al
O3 interface control unit A204 is 1 peripheral control unit B
At the same time, the internal peripheral control unit B207 instructs the interface control unit B207 of the 104 to start data transfer between the peripheral control units, while the internal peripheral control unit AIO3 is in the middle of data transfer based on other input/output operations with the main memory 102. If data is being transferred (310), input/output operations between the peripheral control units are made to wait until the data transfer is completed, and when the data transfer is completed, the inner peripheral control unit AlO3 is activated. Make it ready. Thereafter, it waits for a ready status report from the peripheral control unit r3104 (311).

On the other hand, the interface control unit B2 of the peripheral control unit B104
07 is the interface control unit A of the peripheral control unit AlO3
Upon receiving a startup instruction from 204.

The inner peripheral control unit B104 determines whether data is being transferred with the main memory 102 (312).

If data is being transferred, input/output operations between the peripheral control units are made to wait until the data transfer is completed, and when the data transfer is completed, the peripheral control unit B104 is placed in the ready state, and the interface control unit A204 is placed in the ready state. Report something.

The interface control unit A204 of the peripheral control unit AlO3 is the interface control unit B207 of the peripheral control unit B104.
Upon receiving a report that the peripheral control unit B104 is in the ready state, the inner peripheral control unit AlO3 and other peripheral control units B104
After confirming that both are in the ready state, the data bus 106 is sent to the bus SW control unit 202 of the bus control unit 105.
Give cutting instructions. Based on this, the bus SW control unit 202 instructs the bus 5W203 to disconnect the data bus 106, and reports the completion of disconnection to the interface control unit A204 of the peripheral control unit AlO3 (313). Bus 5W
When the data bus 106 is logically disconnected by the data bus 203, the data bus 106 can operate as two independent buses.

The interface control unit A204 of the peripheral control unit AlO3 receives the report of disconnection of the data bus 106 and controls the internal peripheral control unit A.
A data transfer operation between IO3 and other peripheral control unit 8104 is started (314). This data transfer is performed by a control operation between data transfer control unit A205 and data transfer control unit B2O3, and the peripheral device under peripheral control unit AlO3 is transferred. 107→Data buffer A 20 f3→Data bus 106→Data buffer B209→Peripheral device 10 of peripheral control unit B104
7 route or vice versa.

Regarding the address of the data buffer when transferring data to the data buffer in another peripheral control unit.

A method of assigning the processor number of the peripheral control unit to the upper address, or a method of assigning a data buffer address as an extension of the main memory address, etc.

There is.

Even during data transfer between the peripheral control units 103 and 104, data transfer between the CPU 1.01 and the main memory 102 can be executed simultaneously via the data bus 106.

When the data transfer between the peripheral control units 103 and 104 is completed, the interface control unit A204 of one peripheral control unit AlO3
instructs the bus SW control unit 202 of the bus control unit 105 to connect the data bus 106. Bus SW control unit 202
This allows data bus 10 to be connected to bus 5W203.
6 connection (315), peripheral control unit AlO
The interface control unit A204 of No. 3 is connected to the data bus 106.
When it is confirmed that the is connected, it instructs the data transfer control unit A205 to write the input/output operation results (normal termination/abnormal termination, information on the cause in the case of abnormal termination) to the main memory 102, and transfers the data. The control unit A205 writes the output operation result to the main memory 102 via the data bus 106 (316).

After this writing is completed, the interface control unit A20
4 raises an interrupt for the end of input/output operation to CI'''UIOI.

[Effects of the Invention] As explained above, according to the present invention, data transfer between peripheral control units is realized by passing through a data buffer provided in the peripheral control unit without going through the main memory, and By disconnecting/connecting the data bus between a group of main memory and a group of multiple peripheral control units, it is possible to simultaneously execute data transfer between peripheral control units and data transfer between the CPU and main memory. This makes it easy to reduce main memory access traffic and improve system throughput by parallelizing data transfer.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of an embodiment of an information processing device to which the method of the present invention is applied, and FIG. 2 is a bus control section in FIG.
FIG. 3, a detailed configuration diagram of the peripheral control section, is a diagram showing the operational flow when input/output operations are executed in the embodiment. 101...CPU, 102...Main memory, 1
03.104... Peripheral control unit, 105... Bus control unit, 106... Data bus, 107... Peripheral device, 201... Bus allocation control unit. 202...Bus allocation control unit, 203...Bus SW
, 204.207...interface control unit, 205
．． 208...Data transfer control unit, 206.209...
- Data buffer, 210...control line.

Claims (1)

[Claims] (1) Consists of a central processing unit, main memory, and multiple peripheral control units that control peripheral devices, each connected to the same bus, and data between the central processing unit and the main memory, and between the peripheral control unit and the main memory. In an information processing device that performs transfer via the bus, there is a method for disconnecting and disconnecting the bus between a first group consisting of a central processing unit and main memory and a second group consisting of a plurality of peripheral control units.
A means for controlling the connection is provided, and when the bus is connected, data transfer between the central processing unit and the main memory or between the peripheral control unit and the main memory can be executed exclusively, and when the bus is disconnected, the central processing unit 1. A data transfer control method characterized in that data transfer between a main memory and a main memory and a data transfer between one peripheral control section and another peripheral control section can be executed independently.