JPH02272666A - Dma transfer control circuit - Google Patents

Abstract

PURPOSE:To efficiently read and write data by transferring data between plural I/O devices and a main storage device through a buffer memory connected between both the devices and storing transfer data and the device numbers of the I/O devices in the buffer memory. CONSTITUTION:When data transfer between the main storage device 2 and the I/O devices 4 to 6 is required, the I/O devices 4 to 6 send the data to be transferred and information indicating the device numbers of the I/O devices 4 to 6 indicate which I/O devices 4 to 6 transfer the data to an FIFO type buffer memory 7. When the data are transferred from the I/O devices 4, to 6, the buffer memory 7 outputs a DMA(direct memory access) transfer request to a direct memory access controller(DMAC) and DMA transfer is started between the main storage device 2 and the buffer memory 7. Even when DMA transfer requests are outputted from plural I/O devices 4 to 6, the queuing time can be reduced and efficient data transfer can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an I) MA transfer control system in a personal computer system or the like.

[Conventional technology]

Information processing devices such as personal computers usually require data transfer between an input/output device and a storage device. When such data transfer is performed by a CPU program, several instruction cycles are required for the processing. Furthermore, c
p The time required for the LJ to fetch an instruction and the time required to check the transfer request of the input/output device, and the time required to transfer one piece of data depends on the amount of time actually required between the storage device and the input/output device. This becomes extremely long compared to the time it takes to transfer data. Therefore, a DMA transfer method is used in which only the originally necessary data transfer between the storage device and the input/output device is performed directly without going through the CPU.

The conventional DMA transfer method will be explained below based on the drawings.

FIG. 2 is a block diagram showing a conventional DMA transfer method. 1 is a CPU, 2 is a main storage device, and 3 is an L) MAC, which are connected to input/output devices 4 to 6 via an address bus 100 and a data bus 1 old. Here, an explanation will be given assuming that there are three input/output devices, and data is transferred from the input/output devices to the main storage device. l)
The MAC 3 and each input/output device are connected by control lines 11 to 13, and these transmit signals for performing DMA transfer between the main storage device 2 and the input/output devices 4 to 6, respectively. That is, a DMA transfer request signal is output from the input/output device to the DMAC 5, and a DMA transfer permission signal is provided from the DMA c 3 to the input/output device. In addition, the DMAC 5 issues a bus release request signal to the CPU through the control line 10 in order to obtain the right to use the bus.
I receives this and sends a bus release permission signal l) M A C
Give to 3. Data transfer is performed using two command signals.

In other words, IO reads data from the input/output device.
A control line 20 represents an RC signal, and a control line 21 represents an M W 'l' C signal for writing data into the main memory rfi2.

Next, the actual DMA transfer operation will be explained using FIG.

FIG. 3 is a time chart I showing the operation of DMA transfer in the circuit shown in FIG. Here, the description will be made assuming that transfer between the three input/output devices 4 to 6 and the main storage device 2 is performed in order. Usually address bus 100,
The CPU 1 has the right to use the data bus 101 and uses this to exchange data with the main storage device 2 and execute various instructions according to the programs stored in the main storage device 2. .

However, as shown in FIG. 3(a), the input/output devices δ to l
) M A transfer request signal D RQ n = “1” is DM
When it is output to AC3, DMAC5 receives it and outputs it to CP.
A bus release request signal HRQ=”I II is output to the UI. (Figure 3 (b)) Here, n means the number of the input/output device, and = o
, 1.2, etc. First, assume that n = 0 transfer is performed. C1) When Ul accepts the HRQ, it connects address bus 100 and data bus 1 at a convenient time for its operation.
01 is released, and at the same time, a bus release permission signal HLl)A="1" is output to the DMAC 5 as shown in FIG. 3(c). As a result, the CPUI suspends its operation and yields the right to use the bus to the DMAC 5.

In response to this, the DMAC 5 outputs a DMA transfer permission signal DACKn="1" to the input/output device that made the DMA transfer request (FIG. 3(d)), and notifies the input/output device that the DMA transfer is permitted. Address 1 of the main storage device 2 to be DMA transferred is output to the address bus 100 (see Fig. 3(e)
)) Then, the DMAC 5 activates the signal l0RC that instructs data reading from the input/output device, that is, sets it to a "low" level (see FIG. 3(g)).
), read data 1 from the input/output device is data bus 1
01 (FIG. 3(f)).

Further, the DMAC 5 activates the signal MWTC instructing data writing to the main memory device 2 (see FIG. 3).
h)), write the above data to the main storage device 2;

As described above, when one data transfer between the input/output device and the main storage device 2 is completed, the input/output device receives the signal DR.
Qn is set to "0" to notify the DMAC 5 of the end of DMA transfer. I) M A C3 receives this and sends the signal HRQ.
tI: "O"', the right to use the bus is set to CTJ tJ
1, and CP tJ 1 sets the signal HLDA to 0'' and resumes the interrupted process.

When performing a data transfer between another I/O device and the main memory, the I/O device again uses D RQ n (this time n
=, L, etc.) is set to "1", a DMA transfer request is made, and the DMA transfer is started in the same procedure as described above.

In addition, as a related device of this type.

For example, those described in Japanese Unexamined Patent Publication No. 61-6754 can be mentioned.

[Problem to be solved by the invention]

In the conventional method described above, the DMAC transfers data between the main storage device and the input/output device, and high-speed transfer is possible. However, when there are DMA transfer requests from multiple input/output devices, DMAC cannot process them simultaneously.
There is a problem in that input/output devices other than the input/output device whose request has been approved are forced to wait until the transfer is completed. Furthermore, since the input/output device for reading and writing data and the access time to the main storage device are different, there is a problem in that efficient data transfer cannot be performed.

An object of the present invention is to reduce the waiting time of input/output devices even when there are DMA transfer requests from multiple input/output devices.
The object of the present invention is to provide 1) an MA transfer control system that can perform efficient data transfer.

[II! Means for Solving Problem 1] In order to achieve the above objective, a DMA is installed between the data bus and the input/output device.
The configuration is equipped with an O-type buffer memory that stores the data to be transferred and information encoded with the numbers of multiple input/output devices, and the actual DMA transfer is performed between this DOED0-type buffer memory and the main This is done with the storage device.

[Effect]

When it is necessary to transfer data between main storage and an input/output device, the input/output device first sends the data to be transferred along with the number of the input/output device to indicate which input/output device the data is coming from. Sends the information represented to the F" I F O type buffer memory. At this time, it is okay for data from multiple input/output devices to be discarded to the buffer memory.
When the IFO type buffer memory receives data from the input/output device, 1) it makes a DMA transfer request to the MAC, and performs the DMA transfer between the main storage device and the FIFO type buffer memory. is started.

〔Example〕

Embodiments of the present invention will now be described based on the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. 1
is the CPU, 2 is the main memory, :3 is 1] MAC,
These are address buses 100. They are connected via a data bus 101. What about input/output devices 4-6? ' It is connected to the data bus 101 through the IFO type buffer memory 7. The O-type buffer memory 7 has a buffer 71 (hereinafter referred to as a read buffer) for transferring data from an input/output device to the main memory 2, and a buffer 71 for inputting data from the main memory 2. There is a buffer 72 (hereinafter referred to as a write buffer) for transferring data to an output device.

In the following, a transfer operation from the input/output devices 4 to 6 to the main memory bag fi2 will be explained as an example. The FIFO type buffer memory 7 outputs a DMA transfer request signal via the control line 14. Based on this signal, the decoder 8 decodes which input/output device the data is from and controls the control lines 11 to 1.
It is output as a 4ft DMA transfer request to the DMAC 5 via the 4ft. DMAC34 received this and cpu
In order to obtain the right to use the bus, it issues a bus release request signal through the control line 10, and also receives a bus release permission signal from the CPUI. The control lines 21 and 22 are command signals for data transfer, and the control line 2L is a supplementary signal for writing data into the main storage device 2, and the control line 22
is a F L DC signal for reading data from the F i F' O-type buffer memory 7.

FIG. 4 shows how data sent from the input/output devices 4 to 6 is stored in the read buffer 71. In addition to the data to be DMA transferred from the input/output devices 4 to 6, data encoded with the number of the input/output device to indicate which input/output device the data is from is also stored in the one-stop buffer. Here, the encoded information representing the number of the input/output device is expressed in 2 bits, and "oo" is input/output device 4. "Of" represents the input/output device 5, and I+ 1011 represents the input/output device 6. That is, the data of the input/output devices 4 to 6 are stored in the read buffer 71 in order.

Next, the DMA transfer operation between the read buffer 71 and the main memory bag 2 will be described with reference to FIG. Fourth
As shown in the figure, when data from the input/output device is sent to the read buffer 71, the O-type buffer memory 7 issues a DMA transfer request to the DMAC 5. This signal is sent to the control line 14. Based on this signal, the decoder 8 decodes which input/output device the data is from and outputs it as a DMA transfer request signal to the DMAC 5.As shown in FIG. Since the first data 1 is from the input/output device 4, the control line 11 becomes active.
n = "1" is output to L) MA C3.

(FIG. 5(a)) Here, n corresponds to the decoding result by the decoder 8, and represents the number of the human blade device. Here, first, transfer of n=0 is performed. Thereafter, the operations shown in FIGS. 5(b) to 5(e) follow the same steps as those shown in the prior art. That is, l) M A C3 is CP
The bus release request signal HRQ="1" is output to the UI, and the CPU 1 receives this and outputs the bus release permission signal HLDA="1".
It outputs "1" to give the DMAC 5 the right to use the bus. DMA C:3 notifies that the DMA transfer is permitted, and also outputs address 1 of the main storage device 2 to be transferred to the address bus 100 (the fifth
Figures (b) to (e)).

Next, the DMAC 5 activates the FII (a signal instructing to read data from the O-type buffer memory 7), that is, sets it to a ``low'' level (FIG. 5(g)), thereby reading the read buffer 71. data 1
is output onto the data bus 101 (FIG. 5(g)). Furthermore, the DMAC 5 activates the signal MWTC instructing data writing in the main memory device 2 (FIG. 5(h)).
), writes the above data to the main storage device 2. In this way, the 1
When the first data transfer is completed, the FIFO type buffer memory 7 notifies the end of the DMA transfer and prepares for the first data transfer. The next data 2 stored in the read buffer 71 is transferred in the same manner, and the transfer is repeated until the read buffer is empty.

In general, the access times for reading and writing data to a main memory device and an input/output device are different, with the latter taking longer. This has been a problem in the conventional example. According to this method, actual DMA transfer is performed between the main storage device and the FIFO type buffer memory instead of between the main storage device and the input/output device. Since access to the PIF'O type buffer memory can be performed in about the same time as access to the main memory, there is no difference in access time for reading and writing data, and efficient data transfer can be performed. Then, each time a transfer is performed, the DMAC
5 returned the right to use the bus to the CPUI, and obtained the right to use the bus again in response to the next 1) MΔ transfer request. this is,
This was a problem in DMA transfer of data from multiple input/output devices. However, there are known DMACs that can accept different DMA transfer requests without releasing the bus once the right to use the bus is obtained.

By applying the 1-hydro formula to such a DMAC,
Data from multiple input/output devices can be transferred equally and efficiently. FIG. 6 illustrates one embodiment of such transfer. DM from FIFO type buffer memory
When the DMAC 5 accepts the A transfer request again, the DMA
C performs DMA transfer according to the data from the buffer memory 7, and continues the transfer until there is no more data stored in the buffer memory. Since data from each input/output device is stored in the buffer memory along with information representing the device number, data from a specific input/output device is not kept waiting.

Although the present embodiment has been described above using an example of transfer from an input/output device to a main storage device, the present method can also be applied to the reverse, that is, transfer from a main storage device to an input/output device. Furthermore, in this embodiment, the number of input/output devices is three, but it is clear that this method becomes more effective when there are more input/output devices.

〔Effect of the invention〕

According to the present invention, data transfer between the main output device and the main storage device is performed via a buffer memory provided therebetween,
Since the transfer data and information representing the number of the input/output device are stored in this buffer memory, data can be read and written efficiently, and transfer from a plurality of input/output devices can be performed equally.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing a conventional method, and Fig. 3 is a block diagram showing an embodiment of the present invention.
FIG. 4 is an explanatory diagram showing how data is stored in the read buffer. FIG. 5 is a time chart for explaining the DMA transfer operation according to this method. FIG. 6 is a time chart for explaining one embodiment of this method. 1...CPU, 2...Main storage, 3...I)
M.A.C. 4.5.6...I/O device, 7...k='IdoO
Type buffer memo 1c8...decoder, ]00...address bus. 101...Data bus.

Claims (1)

[Claims] 1. A CPU (Central Processing Unit), a main storage device that stores programs and data for controlling its operation, and the CPU
An address bus and a data bus that connect U and the main storage device, a DMAC (direct memory access controller) for controlling direct memory access transfer via the data bus, and a plurality of input/outputs. a DMA transfer control circuit comprising a device, an F for storing DMA transfer data and information encoded with a number of the input/output device between the data bus and the input/output device;
A DMA transfer control circuit comprising an IFO type buffer memory and performing DMA transfer between the FIFO type buffer memory and the main storage device.