JPH01191248A - Error retry system of channel controller - Google Patents

Abstract

PURPOSE:To automatically execute a retry by transferring access contents stored in an access result buffer to an access request buffer by the control of a signal control part in an interface circuit to a memory to execute the retry of access at the time of return of an error report from the memory. CONSTITUTION:When a signal sent from the memory to a control line 172 indicates error, error is discriminated by a signal control part 17 to generate control signal '1' on a control line 174. Then, driving circuits of buffer mechanisms 12-15 are operated to read out store data, which is stored at the time of access, from a load data buffer 12 and this data is stored in a store data buffer 15 again through a transfer line 122 and a gate circuit 152, and the memory address and the command stored in an end stack 13 are read out and are stored in an address buffer 14 through a transfer line 132 and a gate circuit 145. Thus, the retry is executed.

Description

[Detailed Description of the Invention] [Summary] Regarding a retry method when an error occurs when accessing memory requested by a channel in a channel control device of an information processing device, the present invention relates to a retry method when a channel control device accesses memory. The purpose is to provide an error retry method using a channel control device that automatically performs a retry when an error notification is received, regardless of the channel function. In a channel control device provided in a channel controller, which includes a buffer, a memory, and an interface circuit for the channel, upon receiving a request for accessing the memory from the channel, storing the access contents in the access request buffer;
When a memory access is executed, the access contents are sent to the memory and stored in the access execution buffer, and when an error notification is returned from the memory after the memory access is executed, the above-mentioned information is sent under the control of the signal control unit in the ink face circuit for the memory. The access content stored in the access execution buffer is transferred to the access request buffer and the access is retried.

[Industrial Application Field] The present invention relates to a retry method when an error occurs when executing a memory access requested from a channel in a channel control device of an information processing device.

A channel control device of an information processing device is provided between a plurality of channel devices and a host device such as memory, CPU, SVP (service processor), etc., and the channel control device is equipped with a buffer and communicates with the host device and the channel. It is equipped with an interface for both devices and performs data transfer and control.

Access operations such as stores and loads to the memory executed in response to requests from the channel are executed by the buffer and memory interface circuit of the channel control device via the memory bus, but after the access is executed, the memory is stored from the memory side. , an error signal may be returned indicating that the load operation was not performed normally. In such a case, an error indication signal is sent from the channel control device to the channel, and a retry operation is performed from the channel, but it is desired to shorten the time from the time the error occurs until the retry is executed.

[Conventional technology] FIG. 3 shows a system configuration diagram of a conventional information processing device.

As shown in FIG. 3, each of the plurality of channel devices 36 to 38 has one or more input/output devices (indicated by 10) 391
393, and each channel device 36-38 is connected to one channel control device 35. The channel control device 35 connects to the CPU 31.5VP30 via the common bus 34.
It is connected to a memory (represented by MEM) 32 via a memory bus 33. Each bus consists of a data address bus and a control bus.

FIG. 4 shows a configuration diagram of a conventional example of a channel control device used in the above system.

FIG. 4 shows a configuration mainly consisting of a memory interface, with buses to channels shown on the upper side and memory buses shown on the lower side.

In the figure, 40 is a register that is a channel interface section, 41 to 44 are buffer sections, 41 is a load data buffer that holds data read from memory, and 42 is an end (end) that holds a command that notifies completion.
END) stack, 43 is memory address buffer, 4
4 is a store data buffer, 45 to 48 are memory interface units, 45 and 48 are registers, 46 is an end control unit, and 47 is a request (REQ) control unit.

Channel system? ! IT devices send access requests for multiple channels via a data address bus (hereinafter simply referred to as bus) 4.
00 from the control line 410 and accesses the memory in order. In this case, the address (including the command)
and data (however, the data is only in the case of a store request) are sent to the memory address buffer 4 via the register 40.
3 and stored in the store data buffer 44. In this explanation, it is assumed that a store request is issued from a channel, and when executing an access, the command is taken out from the memory address buffer 43, supplied to the request control unit 47, decoded, and sent to the control line 470 of the memory bus. Outputs a control signal to instruct storage. At the same time, the address and store data from each buffer 43 and 44 are supplied to the register 48 and output to the data bus.

In response, a corresponding store operation is executed in the memory, and when completed, an end signal is output to the control wA 460 and input to the end control unit 46.

In response to this, the end control unit 46 requests the request control unit 47
Create a normal completion notification command by modifying the store command obtained from and store it in the end stack 42,
It is sent from the bus 400 via the gate circuit 420 to the channel of the access request source.

An error occurs when the memory executes this store operation (
If an error occurs in the data, etc.), the memory outputs an end signal and a signal indicating the error to the control line 460. When the end control unit 46 detects this error signal, it sets a flag indicating an error, stores an error notification command in the end stack 42, and sends the bus 400 to the control line 4.
10 to the access request source channel. When the access request source channel receives a normal end command, the access operation ends, but when it receives an error notification command, if the channel is equipped with a retry function, it restarts the previous access and performs a retry. perform an action. If the channel does not have a retry function, perform error processing (error display, etc.).

If the request access from the channel is a load operation,
A memory address and a command instructing a load are received from the bus 400 and a control line 410, and the data read from the memory is stored in the load data buffer 41 and then returned from the bus 400 to the request source channel along with a completion notification command.

[Problems to be Solved by the Invention] As described above, according to the conventional channel control device, there is no problem if the memory operates normally when the memory is accessed, but if an error occurs, teeth,
The channel control device simply creates a command with an error flag and returns it to the corresponding channel, and the channel that receives the command does the following:
If a retry function is provided, the retry operation is executed by a microprogram. For this reason, there is a problem in that not only is there a time loss until a retry is started depending on the channel, but also it takes time to perform a retry operation using a microprogram.

Further, if the channel is not equipped with a retry function, there is a problem in that in the case of an error that is not reproducible, normal operation can be achieved with one retry, but retry cannot be performed.

An object of the present invention is to provide an error retry method by a channel control device that automatically executes a retry regardless of the channel function when the channel control device accesses memory and receives an error notification.

[Means for solving problems] FIG. 1 is a basic configuration diagram of the present invention.

In FIG. 1, 1 represents a channel control device, 2 represents a channel, 3 represents a memory, 11@16.18 in channel 1 represents a register, 12 represents a load data buffer, 13 represents an end stack, 14 represents an address buffer, and 15 represents a Store data buffer 17 represents a signal control section.

The register 11 is an ink face circuit for the channel, and registers 16 and 18 and the signal controller 1
Reference numeral 7 is an ink face circuit for the memory, a load data buffer 12 and an end stack 13 are buffers for accessing, and an address buffer 14 and a store data buffer 15 are buffers for access requests.

In the present invention, when accessing memory, data, addresses, and commands of the access contents are stored in another buffer mechanism in the channel control device, and if an error notification is received from the memory interface, the channel control device does not return to the channel and This is to control the access to be performed again using the access contents stored in advance by the control device.

[Operation] To explain the operation of FIG. 1, a memory access request from a channel is supplied to the buffer mechanism via the register 11 as in the conventional case, and the memory address and command of the access contents are stored in the address buffer 14. Store data (this data does not exist in the case of a load command) is stored in the store data buffer 15.

When an access operation starts for the contents stored in this buffer mechanism, a memory address and a command are taken out from the address buffer 14, and the command is supplied to the signal control section 17 and the memory address is supplied to the register 18.

At the same time, the address and command are set in the end stack 13 by a newly provided transfer line (bus) 142.

To explain the case where this access requests data to be stored in memory, this access operation causes the store data in the store data buffer 15 to be set in the register 18 through the transfer line (bus) 151. At the same time, a new transfer '4IA153 was established.
and is stored in the load data buffer 12.

Thus, at the time of access, a command supplied to the signal control unit 17 sends a corresponding request signal to the memory to the control signal line 171, and the register 18 sends a memory address and store data to the address/data bus.

A corresponding store operation is performed in the memory 3, and when the operation is completed, an end signal is sent to the control signal line 172. If this signal indicates that the command has ended normally, the signal control unit 17 modifies the command, stores a return signal in the end stack 13, and sends the return signal to the channel from there.

When the signal sent from the memory to the control line 172 indicates an error, the signal control unit 17 identifies the error, and in this case, since it is the -th error, a signal is sent to the control line 174 to execute a retry. Generates an output signal "1".

As a result, buffer mechanisms (12 to 15) (not shown)
The drive circuit operates to read out the store data stored at the time of access from the load data buffer 12 and store it again in the store data buffer 15 through the transfer line 122 and the gate circuit 152, and at the same time read out the store data stored in the end stack 13. The memory address and command are read out and stored in the address buffer 14 through the transfer line 132 and gate circuit 145.

Note that even if a return signal is generated at this time, the gate circuit 13
3, transmission is prohibited and is not sent to the channel.

When the access contents are stored in each buffer 14.15,
The memory is accessed again, and if normal operation is performed, the return signal created by the signal control unit 17 is sent from the end stack 13 to the corresponding channel.

If an error occurs even with this retry operation, the signal control unit 17 does not execute any more retries (does not generate "1" on the control line 174), sets a flag indicating the error, and creates a return signal. , end stack 1
3 to the channel.

[Example] FIG. 2 shows a configuration diagram of an embodiment of the present invention.

In Fig. 2, 20, 25.2 days are registers, 21 is a load data buffer, 22 is an end stack, 23 is a memory address buffer, 24 is a store data buffer, 26 is an end control section, and 27 is a request control section. , thick lines in the figure represent data lines, and thin lines represent control signal lines.

The upper part of FIG. 2 is connected to a channel (not shown) via a bus, and the lower part is connected to a memory via a memory bus.

Although the operation of the embodiment is basically the same as that shown in FIG. 1, the store operation will be briefly explained below.

An access request from the chaffle is sent via the register 20, and the memory address and command are sent to the memory address buffer 23.
The store data is stored in the store data buffer 24. In that case, store data (8 bytes) (indicated by 8B) are input from the bus in parallel. In the access operation, store data is transferred from the store data buffer 24 to the transfer line 242.2.
43 (the transfer path 281 has a width of 4 bytes) is sent to the register 28 through the selection circuit 280, and at the same time, a total of 8 bytes, 4 bytes each, are transferred to the load data buffer 21 and stored.

On the other hand, addresses and commands are stored in memory address buffer 2.
3, the address is sent to the register 28, the command is sent to the request control unit 27, and at the same time, the address and command are stored in the end stack 22.

Then, the command is sent from the request control unit 27 to the command unit 264 of the end control unit 26, and
Is the store request signal controlled by decoding the command? 11
line 270 and simultaneously the data and address to the memory bus, the memory performs the requested store operation.

When an END signal is sent from the memory via the control line 260, the decoder 262 of the end control section 26 decodes it and outputs it to the response section 261.

The response section 261 modifies the contents of the command section 264 sent at the time of access and turns on a specific bit indicating normal termination at the exit of the end stack 22. The modified command is sent to the channel as a return signal via the gate 202 and the selection circuit 201.

When an ERR signal indicating an error is sent from the control line 260 together with the END signal, the decoder of the end control section 26 decodes it and sends an error message to the response section 261.
and also drives the retry section. The retry unit 263 receives the command from the command unit 264 and if the first retry count is not displayed in the command, the control vA 263
6. Generates a "1" output at 265. The control line 266 drives each gate 1-231, 241 to the on state, and the gate 2
02 is turned off, and the control line 265 is sent to a control circuit (not shown) that controls the drive of the buffer mechanisms (21 to 24) to operate each buffer circuit as follows.

That is, the previously stored store data is read from the load data buffer 21 and output to the transfer line, and the end stack 2
The memory address and command stored first are read from 2 and output to the transfer line 222. Since the gate 241 is on, the output store data is manually input to the store data buffer 24 and stored there again.

Also, the output memory address and command are sent to the gate 23.
1 and is stored in the memory address buffer 23.

At this time, the response unit 261 sets an error flag for the contents of the command unit 264 and creates a return signal, but when the return signal is output from the ent stand tank 22 to the bus to the channel in parallel with the retry operation, the gate 202
is off (per control line 266) so it is not sent to the channel.

Once the access contents are stored in the buffers 23 and 24, when the access operation comes, the access is performed in the same way as the first time. If the result is normal termination, a return signal indicating normal termination is generated from the response section of the end control section 26.
When an error occurs again and an ERR signal is sent from the memory, the response section sets an error flag, creates a return signal, outputs it to the end stack 22, and sends it to the end stack 22.
22 to the channel via gate 202.

At this time, the retry section 263 is also driven, but the retry is prohibited by referring to the information from the command section 264. Specifically, for example, when transferring the memory address and command from the end stack 22 to the memory address buffer 23 during the first retry, a specific bit of the command is set to 1'' in the gate 231, and in the retry access operation, the request control unit 27 to end control section 2
Since this is set in the command section 6, when an error occurs during the second access (retry), the retry section 263 detects it and prohibits retry.

The difference is that in the case of an access requesting a load, nothing is stored in the store data buffer, and as a result of the access operation, load data is stored in the load data buffer, and data is transferred from there to the channel.

[Effects of the Invention] According to the present invention, error retries during store access can be performed for all channels with a slight increase in the amount of hardware, and channel load is reduced for non-reproducible errors due to soft errors. can be reduced and time loss can be minimized.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, FIG. 3 is a conventional system configuration diagram, and FIG. 4 is a configuration diagram of a conventional example. In FIG. 1, 1: Channel control device 2: Channel 3: Memory 11.16.18; Register 12: Load data buffer 13: End stack 14 Near address buffer 15; Store data buffer 17: Signal control section

Claims (1)

[Claims] Buffers (12 to 15) and interface circuits (11, 16 to 18) for the memory and the channels are provided between a plurality of channels of an information processing device and a host device such as a memory.
), when a channel control device (1) receives a memory access request from a channel,
The access content is stored in the access request buffer (14, 15)
When memory access is executed, the access contents are sent to the memory and the access execution buffer (12,
13), and when an error notification is returned from the memory after executing the memory access, it is stored in the access execution buffer (12, 13) under the control of the signal control unit (17) in the interface circuit for the memory. An error retry method using a channel control device characterized in that a memory access retry is executed by transferring the access contents to an access request buffer (14, 15).