JPS61133453A - Memory controller - Google Patents

Abstract

PURPOSE:To attain high reliability of the system by constituting the system that duplicated write is attained in the unit iof memory unit through the setting to a floating address register. CONSTITUTION:An address number designated by a program corresponds to a memory unit number and when central processing units 4, 5 and input/output processors 6, 7 access memory devices 1, 2, a floating address register 31 to convert the address number into the memory unit number is provided in a memory controller 3. At the memory access from the central processing units 4, 5, a real address transmitted from the units 4, 5 is converted into the memory unit number by the floating address register 31 and the access is executed for the memory unit. The floating address register 31 consists of entries having a number equal to the maximum number of memory constitution units and corresponds the address number as an address to each entry.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory control device that performs double writing on only a portion of a pair of memory devices and uses a pool area as an individual memory area.

(Prior Art) Duplex systems and multiprocessor systems have traditionally been employed as methods for improving the reliability of computer systems.

BACKGROUND ART Conventionally, as a method for improving reliability in a tightly coupled multiprocessor system in which a plurality of processors operate under the same operating system, techniques such as those described below have been employed. When a failure occurs in the central processing unit of a device that makes up a multiprocessor, first of all, if the failure is an intermittent failure that can perform retry processing such as instruction retry, the central processing unit should be used to repair the failure. Processing 'dj! A Continue. In addition, if the retry fails due to a fixed failure, if you execute the processor IJ IJ +f to transfer the state of the central processing unit at the time of the failure to another normal central processing unit and retry, It is possible to remedy the above failure.

On the other hand, in the case of a failure of the input/output retry IC that performs the input/output transfer fee m between the input/output device d, a retry is first performed at the faulty base, and if that fails, the other This can be saved by retrying the I/O using the I/O interface of the normal I/O processor. In this way, in a multiprocessor system, even if a failure occurs in the central processing unit or input/output processing unit, processing can be continued by switching to the central processing unit, so system failures due to equipment failure are rare. do not have.

If the memory hardware of the main storage device fails, data will be lost.If the lost data is related to an individual job, only that job will be aborted and the system will continue to operate. can do. However, if the memory section involved the core processing of the operating system, the system would inevitably go down. When realizing a highly reliable system using a multiprocessor system as described above, the reliability of the memory system is the biggest problem.

One way to solve this problem is to prepare two memory devices, write the same data to both memory devices, and read the contents of both memories when reading memory, so that even if one memory fails, the other memory is normal. Memories that can store data and methods for double writing have been put into practical use.

(Problem to be solved by the invention) However, in the above case, the memory device requires twice as much hardware, which increases the cost and also means that the maximum memory capacity can only be used by half of the actual implementation size. I'm sorry for the drawbacks mentioned above.

An object of the present invention is to eliminate the above-mentioned drawbacks by performing double writing only on partial memory areas of two memory devices and allowing the pool area to be used as an individual memory area.
MemoIn January, the system went down due to a tornado damage.Memory can be used effectively by performing double writing only in the memory area of the core processing, and by writing singlely in each job area where the job can be aborted even if a failure occurs. Another object of the present invention is to provide a memory control device configured so that a system failure does not occur even in the event of a memory failure.

(Step-a for Solving the Problems) A memory control device according to the present invention is connected to a plurality of central processing units and a plurality of input/output processing bags ψ, and is connected to a pair of memory units composed of a plurality of memory configuration units. 1 and contains a floating address register.

The floating address register is used to convert one real memory address to a different physical address on a pair of memory devices when converting the real memory address from the central processing unit and the slow input/output processing unit to a physical address on a pair of memory devices for each memory configuration unit. If the dual write mode is arbitrarily specified in association with one memory configuration unit on a memory device, and the double write mode is accessed using the specified memory configuration unit, the specified pair of memory devices This is to simultaneously send access requests to the memory configuration units of , select normal data according to the response, and have the access request source respond.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a memory control device according to the present invention together with related devices.

In FIG. 1, 1 and 2 are memory devices, respectively.

3 is a memory control unit, 4.5 is a central processing unit,
6.7 is an input/output processing unit, 11 to 14 and 21 to 24 are memory units, 10.20 is a memory control unit, and 31 is a floating address register.

In FIG. 1 showing an embodiment of the present invention, central processing units 4 and 5 and input/output processing units 6 and 7 are connected to a memory device l via a memory side device 3.

Access 2. Each memory @Hiko1, 2 is a plurality of memory units 11 to 14, respectively.
It consists of 21 to 24. Each memory unit is controlled via a memory controller 10.20 common to the memory devices. Each memory unit is configured into control units such as built-in and detached units.

In addition to the memory unit number physically assigned to each memory unit according to its mounting location, an address number assigned by the program using a real address is defined.

The address number specified by the program is associated with the memory unit number, and when accessing the memory device t1.2 from the central processing unit #4.5 and input/output processing units t6 and 7, the address number is set as the memory unit number. A floating 0 address register 31 for conversion is provided inside the memory control device 3. Central processing unit 4, 5
The real address sent from the central processing unit fi4.5 when accessing the memory from is converted into a memory unit number by the floating address register 31, and access is executed to that memory unit.

The floating address register 31 consists of entries equal to the maximum number of memory constituent units, and the address number is associated with each entry as an address. FIG. 2 is an explanatory diagram showing the format of each entry. In FIG. 2, 34 is a valid bit, and when the valid bit is logic "1", the memory unit corresponding to the corresponding address number is valid. 35 is the double write mode bit, 2
When the overwrite mode pit is at logic ``1#'', the memory units on the memory device 1.2, that is, two memory units are allocated corresponding to the corresponding address number, and double write is performed.

36 and 37 are bits giving the memo display device number and memory unit number respectively set above. Therefore, when specifying the above double writing, a beep)
Since the memory device numbers 36 and 37 are different from each other, it is necessary to designate the memory device numbers 36 and 37 to set different memory devices.

If bit 35 is logic @0, the memory device number and memory unit number are set to bit 36. When accessing the memory, bit 35 is logic "2 in 1s".
When indicating an overwrite, access is issued to both the memory unit indicated by bit 36 and the memory IJ s-nit indicated by bit 37 at the same time.

When the memory access is a read access, the read data read from the memory device 1.2 is checked by the memory control unit #3. If all data are normal and no error is reported from the memory device, the contents of memory device [1 are selected and sent to the access requesting device. If the memory device reports that an error occurred in one of the data, the normal data is sent to the requesting device as usual, and the error is sent to the diagnostic control unit. Report what happened. The diagnostic control section rewrites the contents of the floating address register 31 so as to disconnect the memory unit on the side where the second fault has occurred depending on the above two fault states.

For example, let us assume that when double writing is being performed between the memory unit 11 of the memory device 11 and the memory unit 21 of the memory device ft2, an error occurs on the memory unit 21 side. In this case, f! Bit 35 of the entry corresponding to the mobile address register 31 address number is changed from logic "1" to logic "0", setting bit 36 to indicate normal memory unit 11 writing.

In the case of memory write access, if an error report is sent from the memory device in response to that access, the contents of the floating address register 31 are rewritten in the same way as above, and the memory unit on the normal side remains in single write mode. change.

Further, when the above switching is performed, an error is reported from the diagnostic control section to the service processor, but since such operation is not directly related to the present invention, it will be omitted.

For address numbers for which the double write mode is designated in this manner, double writing is performed in two memory units. Even if an error occurs due to a failure during double writing, the memory unit is simply disconnected and a normal response is sent to the processor requesting the access.Bit 35 is set to logic 10'' and single write is performed. When a failure occurs in the memory unit for a mode address number, an error is reported to the processor requesting access;
Failure part f! by requesting processor J is performed.

Such failure handling typically involves a central processing unit.

1+ will cause a retry to be performed by the input/output processing unit, and if the retry fails, the 9 button will cause a return to be performed by the software.

Therefore, when initializing the floating address register 31, 2! In the t# mode, memory units may be allocated so that the single write mode is used in a processing unit that does not cause the system to go down.

(Effects of the Invention) As explained above, the present invention enables double writing in each memory unit by setting the floating address register, thereby eliminating the need to double write the core part of the memory that would cause a system down due to a memory failure. It is possible to perform multiple writing and single writing for other memory parts, improving memory usage efficiency, minimizing reduction in total memory capacity, and reducing memory I/O.
ii) This has the effect of making the system highly reliable so that it will not go down even if something goes wrong.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating one embodiment of a memory control device according to the present invention, along with associated installations. FIG. 2 is an explanatory diagram showing the format of the contents of the floating address register shown in FIG. 1. 1.2...Memory device 13...Memory control device 4.
5...Central processing unit 1 device 6.7...I/O processing device 10, 20...Memory control section 11-14.21-24...Memory unit 31...
・Floating address register 1G (7, 102, 110-113... signal line 34-
37...Bit area

Claims (1)

[Claims] A memory control device connected to a plurality of central processing units and a plurality of input/output processing units, and connected to a pair of memory devices comprising a plurality of memory configuration units, for controlling double writing of the pair of memory devices. the device, in converting real memory addresses from the plurality of central processing units and the plurality of input/output processing units into physical addresses on the pair of memory devices for each of the memory configuration units; is associated with a plurality of memory constituent units on different memory devices, and a double write mode is arbitrarily specified, and when the double write mode is accessed by the specified memory constituent unit, the specified pair of memory constituent units are A memory control device comprising floating address register means for simultaneously sending access requests to memory constituent units of a memory device, selecting normal data according to the response, and making the access request source respond by selecting normal data.