JP3273191B2 - Data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device for an information processing system, and more particularly, to a data transfer device having a prefetch data buffer for transfer data.

[0002]

2. Description of the Related Art A conventional data transfer apparatus of this type is shown in FIG.
As shown in the figure, the central processing unit 100, the main storage device 20
0, n input / output devices 500 _{1 to} 500 _n , channel control device 1000, n channel devices 2000 _{1 to} 20
Made 00 _n, each channel device had respective input registers 2100, the data transfer control circuit 2300, I / O interface control circuit 2400, a prefetch data buffer 2200 of the same size.

[0003] The channel control unit 1000 receives the output instruction 1 from the central processing unit 100, input-output device designated by the input command 1, for example, the channel device 2000 ₁ connected input and output devices 500 ₁ On the other hand, execution of data transfer is instructed by a signal 9. The channel device 2000 ₁ instructed to execute the data transfer performs the memory request 2 within the capacity of the prefetch data buffer 2200.
4 was carried out, to prepare the transfer data to be transferred to the output device 500 _1. When enough transfer data to start data transfer is available in the prefetch data buffer 2200,
The I / O interface control circuit 2400 controls the input / output device 5
00 to ₁ to transfer the transfer data. When the data transfer is completed, the channel device 2000 ₁
00 to the channel controller 1000 that has received the notification.
Sends an end report 2 of the input / output instruction 1 to the central processing unit 100 and ends the operation of the channel control device 1000.

[0004]

The above-mentioned conventional data transfer apparatus has a fixed-size prefetch data buffer inside each channel device. For this reason, if I / O devices with different transfer performances are connected under the channel device, the prefetch data buffer required for transfer will be prepared according to the I / O devices with high performance, so I / O devices with low transfer performance will be prepared. However, there is a disadvantage that the prefetch data buffer connected to the system is wasted. In addition, in recent years, the speed of input / output devices has been further increased, and the combination of input / output devices having high transfer performance and low input / output devices cannot be avoided. Was. Further, when a failure occurs in the prefetch data buffer of the channel device, there is a disadvantage that the channel device and the input / output device connected thereto become unusable.

SUMMARY OF THE INVENTION It is an object of the present invention to efficiently use a prefetched data buffer according to the transfer performance of an input / output device, and to enable a channel device or an input / output device to use data even when a failure occurs in the prefetched data buffer. A transfer device is provided.

[0006]

According to the present invention, there is provided a data transfer apparatus comprising: a first storage unit in which information indicating data transfer performance of each input / output device is stored in advance; and a plurality of unit areas storing transfer data. And a usage state including a failure flag of each unit area, in which, when an input / output command is received, a corresponding use area of each channel device is arbitrarily assigned from among a plurality of unit areas. A second storage unit in which information indicating is stored, and data output from the prefetch data buffer are checked for each unit area,
When an error is detected, an error detection circuit for notifying the central processing unit and all of the plurality of channel devices, turning on a failure flag of a corresponding unit area in the second storage unit, and receiving an input / output instruction Sometimes, as the use area for data transfer of the channel device to which the corresponding input / output device is connected, the number of unit areas corresponding to the data transfer performance of the input / output device is prefetched by referring to the first and second storage units. And a control unit for selecting and securing the buffer from usable unit areas and controlling data transfer by input / output instructions.

[0007]

When the input / output command is received, the channel controller refers to the data transfer performance of the input / output device and the information on the use status of the unit area stored in the first and second storage units by the control unit. A use area having a size necessary for the input / output instruction is allocated to some of the usable unit areas of the prefetch data buffer, and the area is used to control data transfer to the channel device. During this data transfer, the error detection circuit checks the output data from the prefetched data buffer, and if an error is detected, all data transfer is temporarily stopped by notifying the central processing unit and all the channel devices. When the central processing unit reissues the interrupted data transfer I / O command, the control unit allocates the use area of the prefetch data buffer except for the unit area where the error is detected when referring to the second storage unit. The channel device and the input / output device corresponding to the input / output command can be operated.

[0008]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a data transfer device according to the present invention, and FIG. 2 is a diagram showing a relationship between a prefetch data buffer 302 and a buffer management flag group 305 in the embodiment of FIG.

In this embodiment, as shown in FIG. 1, a central processing unit 100, a main storage device 200, a channel control device 300, n channel devices 400 _{1 to} 400 _n ,
It is composed of n input / output devices 500 _{1 to} 500 _n .

The channel control device 300 includes a prefetch data buffer 302 composed of n unit areas, a failure bit and a busy bit flag of each unit area corresponding to the second storage section, and an assigned channel device number. Are stored, a transfer performance table 308 corresponding to a first storage unit in which transfer performance of each of the input / output devices 500 _{1 to} 500 _n is stored at the time of initial setting, and an output of the prefetch data buffer 302. When the data is inspected and an error is detected, the central processing unit 100 and the channel device 400 ₁
Error detection circuit 309 for sending signals to the control signals 〜400 _n and the channel control circuit 30 corresponding to a control unit for controlling these signals.
1, a data buffer control circuit 303, a data transfer control circuit 304, and two registers 306 and 307.

The central processing unit 100 issues an input / output instruction 1 to the channel control device 300 when an input / output device is used as a device for performing arithmetic processing. In addition, the central processing unit 1
00 gives the transfer performance information 17 of all the input / output devices connected under the control of the channel control device 300 when the channel control device 300 is initialized.

The main storage device 200 has a central processing unit 100
And a channel control device 300, and sends out a one-word memory reply signal 4 for one memory request signal 3 issued from the channel control device 300.

The channel control device 300 is a central processing unit.
100 according to the input / output instruction 1 issued by the
00₁ ~ 400_n To input / output to / from main storage device 200
Device 500₁ ~ 500_n For transferring data to and from
It is. Channel device 400 ₁ , 400_Two , ... 400_n 
Are the input register 401 and the channel data control circuit, respectively.
With path 402 and I / O interface control circuit 403
And the input / output device 500₁, 500_Two , ... 500_n With
A device for controlling the interface;
0, the main storage device 200 and the input / output device 500₁ ~ 5
00_n And data transfer between them.

The channel control circuit 301 decodes and processes the input / output command 1 received from the central processing unit 100. The input / output devices 500 ₁ to 50 designated by the input / output command 1 are provided.
0 _n read transfer performance from the transfer performance table 308, to secure the used area of the prefetch data buffer corresponding transfer performance of the input-output device, further data transfer control circuit 30
4 and a circuit for giving a data transfer instruction to the channel device 400. The prefetch data buffer 302 is a buffer for storing transfer data read from the main storage device 200 prior to transfer, and is a buffer for writing to and reading from an address specified by the data buffer control circuit 303. The data buffer control circuit 303 refers to the buffer management flag group 305 and
The unit area is allocated to the input / output devices 500 _{1 to} 500 _n for transferring data in accordance with the available area 02, and the prefetch data buffer 302 is controlled by the write address signal 16 and the read address signal 15. When the use area of the prefetch data buffer 302 allocated to the input / output devices 500 _{1 to} 500 _n for data transfer becomes full, the data transfer control circuit 304 sends a request suppression signal 1 to the data transfer control circuit 304.
3 is output. The data transfer control circuit 304 accesses the main storage device 200 in accordance with the data transfer instruction signal 8 of the channel control circuit 301. The data transfer control circuit 304 controls each channel device 400 until the data buffer control circuit 303 outputs the request suppression signal 13 for each channel. _The transmission of the memory request signal 3 every _{1 to} 400 _{n is} continued. Each time the memory request signal 3 is transmitted once, the request transmission signal 14 for each channel device is transmitted to the data buffer control circuit 30.
Send to 3.

In the buffer management flag group 305, one flag composed of a channel device number, an in-use bit, and a failure bit is assigned to each unit area of the prefetch data buffer 302. When the area is being used for data transfer, the number of the channel device being used and the used bit "1" are set, and when not used, the used bit is set to "0". The setting / resetting of these flags is performed by the channel control circuit 301.
02 is displayed. The failure bit is set to "0" when normal, and is set to "1" when a failure occurs in the corresponding unit area of the prefetch data buffer 302. Once set, the flag is not reset until failure recovery. It is. The error detection circuit 309 sets the failure bit. The data input register 306 is a register for receiving the memory reply data 4 from the main storage device 200 and writing the same in the prefetch data buffer 302. The data output register 307
The data read from the prefetch data buffer 302 is
This is a register for sending to the channel device specified by the signal 11 of the channel device number. Transfer performance table 3
Reference numeral 08 denotes a memory that stores the transfer performance of all the input / output devices provided from the central processing unit 100 when the channel control device 300 is initialized. Error detection circuit 30
Reference numeral 9 denotes a circuit for detecting a failure of the read data 6 read from the prefetch data buffer 302. When a failure is detected, a failure occurrence area of the prefetch data buffer 302 is determined by the read address signal 15, and an error detection signal 20 is output. Then, the failure bit of the buffer management flag group 305 corresponding to the failure occurrence area is set to “1”.

Next, the prefetch data buffer 3 will be described with reference to FIG.
02 and the buffer management flag group 305 will be described.
One buffer management flag is associated with one unit area of the prefetch data buffer 302. The buffer management flag 305 includes a failure bit indicating whether or not the unit area of the prefetch data buffer 302 has a fault, and a unit area. When the faulty bit and the busy bit are both "0", the corresponding prefetch data buffer 302 has a busy bit indicating whether or not it is busy and a channel device number at the time of use. Indicates that the unit area is available. The channel control circuit 301 determines the required number of unit areas of the prefetch data buffer 302 from the number of words of prefetch data necessary for executing the input / output instruction 1, and determines the channel device number and the busy bit of the channel device to be used prior to the transfer operation. Is set. When the transfer operation is completed, the busy bit is immediately reset.

Next, the operation of this embodiment will be described.

First, when the central processing unit 100 is initialized.
Input / output device connected to the channel control device 300
500₁ ~ 500_n All the transfer performance information
To the controller 300. Next, the channel control device 3
When the input / output instruction 1 is issued to the
The device 300 outputs the input / output instruction 1 by the channel control circuit 301.
An input / output device for decoding and transferring data, for example, 500₁ of
Check transfer performance and use buffer management flags 305
Refers to the middle bit and the failure bit, and
Area where the input / output instruction 1 can be executed based on the usage status of the
Judge whether there is, and execute the I / O instruction 1
Required area of the prefetch data buffer 302 required for
If not, the preprocessing buffer is
Informs impossible due to busy. If input and output
Necessary for execution of input / output instruction 1 if instruction 1 can be executed
To secure the use area of the prefetch data buffer 302,
In the buffer management flag group 305 of the
The channel device number and the busy bit "1" are set. So
And the input / output device 500 specified by the input / output instruction 1 ₁ of
Connected channel device 400₁ For signal line 9
To start the transfer via. Also, the channel control circuit
301 indicates to the data transfer control circuit 304 that the transfer control information 8
To start the memory access. Transfer control information 8
The data transfer control circuit 304 having received the
Start of transmission of signal 3 and make a memory request once.
Request to the data buffer control circuit 303 every time
Signal 14 is sent. The data buffer control circuit 303
With reference to the buffer management flag group 305,
I / O device 500₁ Memory request for data transfer
I / O device 500 inside₁ Prefetch data assigned to
When the used area of the buffer 302 becomes full, the data transfer
Outputs the request suppression signal 13 to the control circuit 304
You. The data transfer control circuit 304 outputs a request suppression signal
13 is received, the transmission of the memory request is suspended.
I do. The data input register 306 stores the received memory
The data of the ply 4 is designated by the write address signal 15.
Address in the prefetch data buffer 302, and
Memory reply to the data buffer control circuit 303
4 is notified. The prefetch data buffer 302
Stored at the address specified by the read address signal 16
Data stored in the memory reply data
307. The data output register 307
When the reply data is received, the signal of the channel device number
Channel device 400 specified by 11₁ Send to
Is completed, data is sent to the data buffer control circuit 303.
A data transmission signal 12 is sent to notify completion of data output. De
The data buffer control circuit 303 includes a data output register 3
07, the data transmission signal 12 is received, and the
I / O device 500₁ Preemption data buffer assigned to
If there is free space in the usage area of the
Stop signal 13 and store data in the data transfer control circuit 304.
Continue sending quests. The above operations are input / output instructions
Repeat until the transfer amount specified in 1 is completed,
When the transfer is completed, the channel control circuit 301
Outputs end report 2 of input / output instruction 1 to device 100
The operation of the channel control device 300 ends.

Further, during data transfer, the error detection circuit 30
9 is the read data 6 of the prefetch data buffer 302
When a failure is detected, the read address signal 16
The corresponding unit area in the prefetch data buffer 302 is determined, and the failure bit of the corresponding buffer management flag group 305 is set. Also, all the channel devices 400 _{1 to} 400 _n under the control of the channel control device 300 are notified of the stop of the data transfer due to the error, and at the same time, the central processing unit 100 is notified that the prefetch data buffer 302 has detected the error. . Central processing unit 100 notified
Resets the channel controller 300 again and issues again all the I / O instructions 1 whose data transfer has been suspended. At this time, when reserving the used area of the prefetch data buffer 302, the channel control device 300 should not be able to reserve the unit area in which the failure bit of the data buffer management flag group 305 is set as in the busy state. Thus, the prefetch data buffer 302 is reallocated without using the failure area.

The data transfer device of this embodiment has n units.
One prefetch data buffer 302 having an area
And n channel devices 4 provided in the channel control device 300.
00 ₁ ~ 400_n In and out and connected to them
Force device 500₁ ~ 500_n According to each transfer performance
Allocate the required number of unit areas each time an I / O instruction is received
Output data from the unit area
Inspection at 309, when an error failure occurs, its unit
The area is prohibited to use.
All channels, including those that control
Device 2000 ₁ ~ 2000_n Is provided for each
Large-capacity data buffer 2200 for high-speed transfer
Is unnecessary, and the unit of the prefetch data buffer 302
Use other available unit area in case of area failure
The channel device 400₁~ 400_n And entry and exit
Force device 500₁~ 500_n Data transfer to
You.

As described above, according to the present invention, the prefetch data buffers of a plurality of channel devices to which input / output devices having different transfer performances are connected are intensively shared, and according to the transfer performance of the input / output devices. By variably allocating the use amount of the prefetch data buffer, the prefetch data buffer circuit dedicated to each channel device can be reduced, and the I / O device having high transfer performance and the low I / O can be realized without being conscious of the transfer performance of the channel device. The device can be freely connected and the prefetch data buffer can be used efficiently without waste. Further, even if a failure occurs in a part of the prefetch data buffer, it is possible to prevent the channel device from being disabled on the spot, thereby improving the reliability of the device.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a data transfer device according to the present invention.

FIG. 2 is a diagram showing a relationship between a prefetch data buffer 302 and a data buffer management flag group 305 in FIG.

FIG. 3 is a block diagram of one embodiment of a conventional data transfer device.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 central processing unit 200 main storage device 300 channel control device 301 channel control circuit 302 prefetch data buffer 303 data buffer control circuit 304 data transfer control circuit 305 data buffer circuit flag group 306 data input register 307 data output register 308 transfer performance table 309 error Detection circuit 400 _{1 to} 400 _n channel device 401 input register 402 channel data control circuit 403 I / O interface control circuit 500 _{1 to} 500 _n input / output device 1 input / output command signal 2 end report signal 3 memory request signal 4 memory reply signal 5 Memory reply data 6 Prefetch data buffer output data 7 Transfer output data 8 Data transfer instruction signal 9 Transfer instruction signal 10 Buffer usage status display signal 11 Channel Reference number 12 Data transmission signal 13 Request suppression signal 14 Request transmission signal 15 Read address 16 Write address 17 I / O device transfer performance information 18 I / O device designation 19 I / O device transfer performance 20 Error detection signal 21 Memory reply reception signal 22 Data transfer Stop signal 23 Error report 24 Channel memory request

Claims (1)

(57) [Claims] 1. A plurality of input / output devices, a plurality of channel devices to which the input / output devices are connected, a central processing unit, a main storage device, and a connection between the channel device and the main storage device. A data transfer device for an information processing system, comprising: a channel control device that controls data transfer between the input and output devices; wherein the channel control device has a first storage in which information indicating a data transfer performance of each of the input / output devices is stored in advance. And a plurality of unit areas for storing transfer data, and one prefetched data in which a use area of each channel device corresponding to an input / output instruction is arbitrarily allocated from among the plurality of unit areas. A buffer, a second storage unit in which information indicating a use state including a failure flag of each unit area is stored, and data output from the prefetch data buffer. Inspection is performed for each location area, and when an error is detected, the error is notified to the central processing unit and all of the plurality of channel devices, and an error flag for turning on a failure flag of the corresponding unit area in the second storage unit. A detection circuit, and as a use area for data transfer of a channel device to which the corresponding input / output device is connected when receiving the input / output command, referring to the first and second storage units, A controller for selecting and securing a number of unit areas according to the data transfer performance from among the available unit areas of the prefetch data buffer, and controlling data transfer by the input / output command. Transfer device.