JP3364751B2 - Data transfer system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of channel devices to which input / output devices are respectively connected, and an instruction for data transfer of memory reply data read from a storage device. And a channel control device for transferring the data to a transfer destination input / output device specified by the input / output command. 2. Description of the Related Art FIG. 3 shows a conventional data transfer system.
This will be described with reference to FIG. The data transfer system shown in FIG. 3 has n channel devices 900 under the control of a channel control device 800.
₁ to 900 _n are those of structure were connected, respectively to each channel unit 900 ₁ to 900 _n, input-output device 10
00 ₁ ~1000 _n is connected. Each of the channel devices 900 _{1 to} 900 _n
Have the same configuration, and each has a main storage device 70.
0 reply data from is stored, and a prefetch data buffer 903 ₁ ~903 _n fixed-size. In such a data transfer device, when data is transferred between the main storage device 700 and each of the input / output devices 1000 _{1 to} 1000 _n , an input / output command is issued from the central processing unit 600 and the input / output command is issued. The channel control device that received the command instructs the channel device 900 to which the input / output device specified by the input / output command is connected to execute data transfer. The channel device 900 instructed to execute the data transfer makes a memory request within the capacity of the prefetch data buffer 903, and the input / output device 10
Prepare transfer data to be transferred to 00. Transfer data sufficient to start data transfer is stored in the prefetch data buffer 9.
03, the I / O interface control circuit 9
04 transfers the transfer data to the input / output device 1000. When the data transfer is completed, the channel device 900 notifies the channel controller 800, and the channel controller 800 having received the notification notifies the central processing unit 600 of an end report indicating the end of the data transfer related to the input / output command. Then, the operation of the channel control device 800 ends. However, in the conventional data transfer system described above, the prefetch data buffer provided inside each channel device is of a fixed size, and the transfer performance differs under the channel device. When an I / O device is connected, a prefetch data buffer necessary for data transfer by an I / O device with high transfer performance is prepared, so when performing data transfer to an I / O device with low transfer performance, There is a problem that the prefetch data buffer is wasted. Further, in recent data transfer systems, the speed has been further increased and the combination of an input / output device having a high transfer performance and an input / output device having a low transfer performance cannot be avoided. Therefore, there is a problem that the waste of the prefetched data buffer is also increasing. Further, when a failure occurs in the prefetch data buffer of the channel device, the channel device becomes unusable. SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the related art, and can efficiently use a prefetch data buffer and perform highly reliable data transfer.
It is intended to provide a data transfer system. According to the present invention, a plurality of channel devices to which input / output devices are respectively connected, and memory reply data read from a storage device are input / output instructions for inputting data. In a data transfer system having a channel control device for transferring data to a designated transfer destination input / output device, the channel control device has a data holding area divided into a plurality of unit areas, and a spare unit area for occurrence of a failure is provided. Corresponding to each unit area of the prefetch data buffer, in-use information indicating whether or not the memory reply data is stored in the unit area, and a memory stored in the unit area. Input / output information indicating a destination input / output device of reply data,
When a failure occurs in the unit area, failure information indicating use prohibition of the unit area is recorded. A data buffer management flag group including a plurality of data buffer management flags, and the data transfer performance of each of the input / output devices is A transfer performance table stored in advance and, when the input / output instruction is issued, extracting a data transfer performance corresponding to the transfer destination input / output device from the transfer performance table, and performing the prefetch according to the data transfer performance. The in-use bit and the input / output device information are set in the data buffer management flag corresponding to the data holding area of the data buffer, and when a failure occurs in the used prefetch data buffer unit area, the data buffer management of the spare unit area is performed. A channel control circuit for setting a used bit and input / output device information to a flag;
Referring to the data buffer management flag group, the address indicating the unit area of the prefetch data buffer related to the data buffer management flag for which the busy bit is set for the transfer destination input / output device of the memory reply data,
A prefetch data buffer control circuit for designating a write address of the memory reply data to the prefetch data buffer and designating a read address for reading the memory reply data already held in the prefetch data buffer; Referring to the memory reply data read from the buffer, it is checked whether or not the memory reply data is normal. If an error has occurred, the memory reply data is read from the unit area corresponding to the read address from which the memory reply data was read. An error detection circuit that records the failure information in a data buffer management flag, wherein each of the data buffer management flags in the data buffer management flag group of the channel control device has a failure in a unit area of the prefetched data buffer. At the occurrence of Fault information indicating the disabling of the unit region is fault bit is provided to be set, further,
The channel control device refers to the memory reply data read from the prefetch data buffer, checks whether the memory reply data is normal, and when an error occurs, the memory reply data is read. An error detection circuit for setting the fault information in a data buffer management flag relating to the unit area corresponding to the read address is provided, and a spare unit area for occurrence of a fault is provided in the prefetch data buffer of the channel control device. The channel control circuit of the channel control device,
When a failure occurs in the used prefetch data buffer unit area, a used bit and input / output device information may be set in the data buffer management flag of the spare unit area. According to the data transfer system of the present invention, the data holding area of the prefetch data buffer provided in the channel control device is divided and used in an amount corresponding to the transfer performance of the input / output device for performing data transfer. Therefore, the prefetch data buffer can be used efficiently even in a system where input / output devices having different transfer performances coexist. Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the data transfer system of the present invention. The data transfer system according to the present embodiment includes a central processing unit 100, a main storage device 200, a channel control device 300, and n channel devices 400 ₁ to which input / output devices 500 _{1 to} 500 _n are connected. and a to 400 _n, input-output device and the main storage device 200 500
Data transfer is performed between _{1 and} 500 _n . The central processing unit 100 performs arithmetic processing, and performs a channel control unit 3 when performing input / output processing.
Issue input / output instruction 1 for 00. In addition, when the channel control device 300 is initialized, the channel control device 30
The transfer performance information 17 about all the input / output devices connected under 0 is given to the channel control device 300. The main storage device 200 stores the central processing unit 100
And a channel control device 300, and sends a one-word memory reply 4 for one memory request 3 issued from the channel control device 300. The channel control device 300 controls each of the channel devices 400 _{1 to} 400 _n in accordance with the input / output command 1 issued by the central processing unit 100, and connects the main storage device 200 with the input / output devices 500 _{1 to} 500 _n. Is a device for transferring data. The channel device 400 ₁ to 400 _n is a device for controlling an interface with input and output devices 500 ₁ to 500 _n, at the direction of the channel control unit 300 and the main storage device 200 output device 500 ₁ and to 500 _n Is performed during the data transfer. Here, the configuration of the channel control device 300 will be described. The channel control device 300 of this embodiment includes a channel control circuit 301, a prefetch data buffer 302, a prefetch data buffer control circuit 303, a data transfer control circuit 304, a data buffer management flag group 305, a data input register 306, and a data output. Register 307, input / output device transfer performance table 308, and error detection circuit 30
9 is provided. The input / output device transfer performance table 308 stores transfer performance information 17 of each of the input / output devices 500 _{1 to} 500 _n transferred from the central processing unit 100 at the time of initialization. The prefetch data buffer 302 is a buffer for storing transfer data read from the main storage device 200 prior to data transfer, and is designated by a read address 15 and a write address 16 issued by the prefetch data buffer control circuit 303. Reading and writing of transfer data are performed on the unit area. The data buffer management flag group 305 corresponds to one prefetch data buffer management flag per unit area of the prefetch data buffer 302. Here, each prefetch data buffer management flag of the data buffer management flag group 305 will be described with reference to FIG. FIG. 2 is a diagram showing the relationship between the prefetch data buffer management flag and the unit area of the prefetch data buffer 302. The prefetch data buffer management flag of the present embodiment includes a failure bit indicating whether or not a unit area of the prefetch data buffer 302 has a fault, and a busy bit indicating whether or not the unit area is being used. , A channel device number indicating the channel device in use. When both the failure bit and the busy bit are "0", it indicates that the corresponding unit area of the prefetch data buffer 302 is available. The prefetch data buffer 302 has a spare unit area for the occurrence of a failure, and the spare unit area usually has a busy bit of “1” for use when a failure occurs.
(Unusable state). When a failure occurs in the unit area of the prefetch data buffer 302, the error detection circuit 309 sets the error detection information 20 ("1") in the failure bit. This fault bit is a flag that is not reset once set. The channel control circuit 301 is a circuit that decodes and processes the input / output command 1 from the central processing unit 100. The designated input / output device information 18 indicating the input / output device specified by the input / output command 1 The transfer performance information 19 of the input / output device is read from the input / output device transfer performance table 308 based on the
2 Use unit area is secured. For securing the unit area to be used in the prefetch data buffer 302, the channel control circuit 301
The use status (use status display signal 10) of the prefetch data buffer 302 is monitored with reference to the data buffer management flag group 305, and when executing the input / output instruction 1, the prefetch data is calculated from the number of words of the prefetch data required. The required number of unit areas of the buffer 302 is determined. Then, the channel device number of the channel device to be used and the busy bit are set in the prefetch data buffer management flag corresponding to the required unit area. Also, the channel control circuit 301
Supplies a data transfer instruction 8 to the data transfer control circuit 304. Further, after the use unit area of the prefetch data buffer 302 is secured, a transfer start instruction 9 is sent to the corresponding channel device, and when the data transfer of the transfer amount specified by the input / output instruction 1 is completed, the central processing An end report 2 is sent to the device 100. The prefetch data buffer control circuit 303
Referring to the data buffer management flag group 305, the prefetch data buffer 30
A read address 15 and a write address 16 are designated for 2. Read address 15, write address 16
Is transmitted after receiving the memory reply reception signal 21 from the data input register 306. Further, a channel device corresponding to the input / output device to which data is transferred, that is, the channel device number recorded in the data buffer management flag in use is transmitted to the data output register 307 as channel device number information 11. When the use status display signal 10 indicates that the unit area of the prefetch data buffer 302 assigned to the input / output device for transferring data is full, the data transfer control circuit 304 sends a request inhibition signal 13 Is output. The data transfer control circuit 304 accesses the main storage device 200 in accordance with the data transfer instruction 8 from the channel control circuit 301. The prefetch data buffer control circuit 303 outputs the request suppression signal 13 for each channel device. The memory request 3 for each channel device is continuously transmitted to the main storage device 200 until the main storage device 200 is transmitted. Further, each time the memory request 3 is transmitted once, the request transmission signal 14 for each channel device is transmitted to the prefetch data buffer control circuit 303. The data input register 306 is a register for writing the memory reply data 4 from the main storage device 200 into the prefetch data buffer 302. When the memory reply data 4 is received, the prefetch data buffer control circuit 303 A memory reply reception signal 21 is sent out. The data output register 307 stores the data read from the prefetch data buffer 302 in the channel device number information 1 from the prefetch data buffer control circuit 303.
This is a register for sending to the channel device designated by 1. When the data sending is completed, it sends a data sending completion signal 12 to the prefetch data buffer control circuit 303. The error detection circuit 309 detects a failure by referring to the read data 6 read from the prefetch data buffer 302. If a failure is detected once, the error occurrence area of the prefetch data buffer 302 is read from the read address 15. Judgment is made, and an error detection signal 20 is issued to set “1” to the failure bit of the data buffer management flag group 305 corresponding to the failure occurrence area. Also, when a failure occurs,
It sends an error report 23 to the central processing unit 100, and sends the data transfer interruption signal 22 to the channel device 400 ₁ to 400 _n. Next, the operation of this embodiment will be described. First, the central processing unit 100 gives the channel control device 300 all the transfer performances of the input / output devices connected under the channel control device 300 at the time of initialization. Thereafter, when an input / output command is issued from the central processing unit 100, the channel control device 300 decodes the input / output command 1 by the channel control circuit 301 and recognizes the input / output device which performs data transfer. Check the transfer performance of the output device. Subsequently, the channel control circuit 301 refers to the in-use bit and the failure bit of the prefetch data buffer management flag group 305 and determines the unit area available for executing the input / output instruction 1 based on the use status of the prefetch data buffer 302. It is determined whether or not is empty. As a result, if the used unit area of the prefetch data buffer 302 necessary for executing the input / output instruction 1 is insufficient, the central processing unit 100 is notified that the execution is impossible due to the prefetch buffer BUSY. On the other hand, when the input / output instruction 1 can be executed,
The channel control circuit 301 sets the channel device number and the used bit “1” in the prefetch data buffer management flag group 305.
Is set, and a unit area for use of the prefetch data buffer 302 necessary for executing the input / output instruction 1 is secured. Then, the channel control circuit 301 issues a transfer start instruction 9 to the channel device to which the input / output device specified by the input / output instruction 1 is connected, and gives the data transfer instruction 8 to the data transfer control circuit 304, Start access. The data transfer control circuit 304 receiving the data transfer instruction 8 starts sending the memory request 3 and
Each time a memory request is made, a request sending signal 14 is sent to the prefetch data buffer control circuit 303. The prefetch data buffer control circuit 303, having received the request transmission signal 14, refers to the prefetch data buffer management flag group 305 and allocates memory reply data for the memory request of the input / output device during data transfer to the input / output device. Prefetched data buffer 3
When the use unit area 02 becomes full, the request suppression signal 13 is output to the data transfer control circuit 304. The data transfer control circuit 304 that has received the request suppression signal 13 temporarily stops sending the memory request 3. On the other hand, when the memory request 3 is accepted, the main memory 200 for the memory request 3 is received.
Is received by the data input register 306. At this time, the memory reply reception signal 21 is transmitted from the data input register 306 to the prefetch data buffer control circuit 303. When the prefetch data buffer control circuit 303 receives the memory reply reception signal 21, the prefetch data buffer control circuit 303 sends the read address 15 and the write address 16 to the prefetch data buffer 302, whereby the memory reply 4 becomes the memory reply data 5. Is stored in the area specified by the write address 16,
Data (read data 6) in the area designated by read address 15 is read, and data output register 307 is read.
Is stored in When the data output register 307 receives the read data 6, the prefetch data buffer control circuit 30
3 is transmitted as transfer data 7 to the channel device specified by the channel device number information 11 and, when the transmission is completed, a data transmission completion signal 12 for notifying completion of data output is transmitted to the prefetch data buffer control circuit 303. I do. The prefetch data buffer control circuit 30
3 is transmitting the request suppression signal 13, and receives the data transmission completion signal 12 from the data output register 307 to create a free space in the use unit area of the prefetch data buffer 302 allocated to the input / output device during data transfer. Then, the transmission of the request suppression signal 13 is stopped, and the data transfer control circuit 304 restarts the transmission of the memory request 3. When the above operation is repeated until the transfer amount specified by the input / output instruction 1 is completed, and the data transfer is completed, the channel control circuit 301 outputs the end report 2 of the input / output instruction 1 to the central processing unit 100. Then, the operation of the channel control device 300 ends. When the error detection circuit 309 detects an error in the read data 6 of the prefetch data buffer 302 during the data transfer, the unit area of the prefetch data buffer 302 in which a failure is considered to have occurred from the read address 15 of the read data 6 Is determined, and the failure bit of the corresponding buffer management flag group 305 is set. At the same time, the in-use bit of the flag of the spare unit area used when a failure occurs is reset. Also, a data transfer stop signal 22 indicating “stop data transfer” due to an error is issued to all the channel devices 400 _{1 to} 400 _n under the control of the channel control device 300, and the prefetch data buffer 302 sends the data to the central processing unit 100. Error report 2 indicating the detection of an error
Notify 3. The central processing unit 100 which has received the error occurrence report 23 resets the channel control unit 300 again and issues all the input / output instructions 1 whose data transfer has been stopped again. In this case, when the channel control device 300 secures a unit area to be used in the prefetch data buffer 302, the unit area in which the failure bit of the data buffer management flag group 305 is set cannot be used as in the BUSY state. The area of the spare prefetch data buffer 302 is used. By setting the flag of the spare unit area, reallocation is performed using the unit area of the spare prefetch data buffer 302 without using the fault area. As described above, according to the present invention, the following effects can be obtained. (1) A plurality of channel devices to which input / output devices having different transfer capacities are connected share a prefetch data buffer, and the amount of use of the prefetch data buffer depends on the transfer capability of the input / output device performing the transfer operation. Can be set,
The prefetch data buffer can be efficiently shared between input / output devices having different transfer performances, and the hardware can be significantly reduced. (2) In recent years, input / output devices have been increasingly speeded up and competition between input / output devices having high transfer performance and input / output devices having low transfer performance has increased. Because the size of the data holding area of the data buffer is variable, if a channel device that supports high-speed transfer is prepared, I / O devices with high transfer performance and low I / O devices can be used without being aware of the transfer performance of the channel device. It can be connected freely, and there is no waste in the prefetch data buffer. (3) Even if a failure occurs in a part of the prefetch data buffer, it is possible to prevent the channel device from being disabled on the spot, thereby improving the reliability of the device.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of a data transfer system of the present invention. FIG. 2 is a diagram illustrating an example of a data buffer management flag group. FIG. 3 is a block diagram illustrating an example of a conventional data transfer system. DESCRIPTION OF SYMBOLS 100 Central processing unit 200 Main storage unit 300 Channel control unit 301 Channel control circuit 302 Prefetch data buffer 303 Prefetch data buffer control circuit 304 Data transfer control circuit 305 Data buffer management flag group 306 Data input register 307 Data output register 308 I / O device transfer performance table 309 Error detection circuit 400 Channel device 500 I / O device

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-208153 (JP, A) JP-A-63-20647 (JP, A) JP-A-63-20648 (JP, A) JP-A-2-2 100739 (JP, A) JP-A-4-361348 (JP, A) JP-A-4-364556 (JP, A) JP-A-5-151138 (JP, A) (58) Fields investigated (Int. Cl. ^7, DB name) G06F 13/00 G06F 13/12 G06F 13/38 G06F 5/06

Claims (1)

(57) Claims 1. A plurality of channel devices to which input / output devices are respectively connected and memory reply data read from a storage device are designated by an input / output command instructing data transfer. A channel control device for transferring data to a transfer destination input / output device, the channel control device comprising: a prefetch device in which a data holding area is divided into a plurality of unit areas, and a spare unit area for use when a failure occurs is provided. A data buffer, corresponding to each unit area of the prefetch data buffer, in-use information indicating whether the memory reply data is stored in the unit area, and memory reply data stored in the unit area. Input / output information indicating the transfer destination input / output device, and fault information indicating that use of the unit area is prohibited when a fault occurs in the unit area. Are recorded, a data buffer management flag group consisting of a plurality of data buffer management flags, a transfer performance table in which the data transfer performance of each of the input / output devices is stored in advance, and when the input / output command is issued, A data transfer performance corresponding to the transfer destination input / output device is extracted from the transfer performance table, and a busy bit and an input bit are set in a data buffer management flag corresponding to the data holding area of the prefetch data buffer according to the data transfer performance. A channel control circuit that sets output device information and sets a busy bit and input / output device information to a data buffer management flag of the spare unit region when a failure occurs in the prefetched data buffer unit region in use; With reference to the data buffer management flag group, the destination input / output device of the memory reply data is An address of a unit area of Sekiru the prefetch data buffer in the data buffer management flag in use bit is set Te,
A prefetch data buffer control circuit that designates a write address of the memory reply data to the prefetch data buffer and specifies a read address for reading the memory reply data already held in the prefetch data buffer; Referring to the memory reply data read from the buffer, it is checked whether or not the memory reply data is normal. If an error has occurred, the memory reply data is stored in the unit area corresponding to the read address from which the memory reply data was read. And an error detection circuit for recording the failure information in a related data buffer management flag.