JPH07306840A - Computer system - Google Patents

Abstract

PURPOSE:To send and receive data in two ways. CONSTITUTION:The computer system which has a 1st CPU 1 and a 2nd CPU 2 and make those CPUs 1 and 2 interchange data with each other is equipped with a 1st storage means 3 through which the 1st CPU 1 writes data and the 2nd CPU 2 reads the data out, a 2nd storage means 4 through which the 2nd CPU 2 writes data and the 1st CPU 1 reads the data out, and an interruption circuit 7 which informs the 2nd CPU 2 that the data are written in the 1st storage means 3 and also informs the 1st CPU 1 that the data are written in the 2nd storage means 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system mounted on a PBX line card or the like and composed of two CPUs.

[0002]

2. Description of the Related Art Conventionally, a PBX line card has a CPU that controls data exchange and a control unit that controls exchange.
And a CPU that sends and receives data to and from the terminal. These two CPUs need to exchange data with each other to operate, and for that reason, the configuration shown in FIG. 5 has been adopted.

That is, a storage unit 103 composed of a memory and the like, a first CPU 101 for transmitting and receiving data to and from a control unit which controls exchange, and a second CPU 102 for transmitting and receiving data to and from a terminal. Connect. The respective CPUs 101, 102 access the storage device 103 via the address assigners 105, 106, respectively,
Data is read and written via the data bus 8.

In this system, the storage device 103
An interrupt circuit 104 is provided to manage the reading and writing of data to and from. Using this interrupt circuit 104, the first CPU 101 and the second CPU 102 operate according to the procedure of the flowchart shown in FIG. First
CPU 101 detects whether or not there is data to be sent to the second CPU 102 (S61), and when data is generated, the first CPU 101 writes the data to the storage device 103 (S62), and then to the interrupt circuit 104. A data read request is written (S64). As a result, the second CPU 1
In 02, the interrupt signal is received from the interrupt circuit 104 at the interrupt input terminal. Therefore, the second CPU 102
Data is read from the storage device 103 (S64), and a status indicating the completion of reading is sent from the status output terminal to the interrupt circuit 104, indicating that the storage device 103 has become empty (S65). Here, it is arbitrary when the first CPU 101 reads the data according to the status sent from the interrupt circuit 104 by the second CPU 102.

On the other hand, in step S61, the second CP
When it is detected that there is no data to be sent to U102, the first CPU 101 reads from the interrupt circuit 104 whether or not there is data to be sent from the second CPU 102 to the first CPU 101. If there is data, a data write request to the storage device 103 is sent to the second CPU 102 via the interrupt circuit 104 (S67). That is, when a data write request is set to the interrupt circuit 104, the interrupt signal of the data write request is sent from the interrupt circuit 104 to the interrupt input terminal of the second CPU 102. In response to the interrupt signal, the CPU 102 writes data to the storage device 103 (S68), and outputs a status indicating the writing of data to the interrupt circuit 104 to output the storage device 10.
The first CPU 101 is notified that there is data in No. 3 (S69). That is, a flag indicating data writing is set in the interrupt circuit 104 by the above-mentioned status transmission, and the first CPU 101 reads from the interrupt circuit 104 to detect the writing of data to the storage device 103 by the second CPU 102. , Data is read from the storage device 103 (S70). Again, the first CPU
When the 101 reads the data according to the status sent from the interrupt circuit 104 by the second CPU 102 and when the data of the storage device 103 is read freely.

[0006]

As described above, in the conventional computer system, one CPU has the command right for writing and reading with respect to the storage device of the other CPU, and the write request by this command right is issued. Otherwise, the other CPU cannot write the data, and in some cases, the data originally to be written in the storage device may be lost. Further, when data is written to the storage device but not read, the data cannot be written until the read is performed, which increases the data write waiting time for any CPU, resulting in efficient data writing. There was a problem that it could not be sent and received.

The present invention has been made to solve the above problems of the conventional computer system, and an object thereof is to provide a computer system which can efficiently perform the data transmission and reception when two CPUs send and receive data. It is to be.

[0008]

Therefore, in the invention described in claim 1, in a computer system having a first CPU and a second CPU, and these CPUs exchange data mutually, A first storage means for the first CPU to write data and the second CPU to read the data; and a second storage means for the second CPU to write the data and the first CPU to read the data. A storage unit and an interrupt for notifying the second CPU that the data has been written to the first storage unit and also notifying the first CPU that the data has been written to the second storage unit. A computer system is configured by including an interrupt circuit that sends an interrupt signal.

According to a second aspect of the invention, in a computer system having a first CPU and a second CPU, and these CPUs exchange data with each other,
The first CPU writes data and the second CP
A first storage means for U to read data, a second storage means for the second CPU to write data and a data to be read by the first CPU, and data of the first storage means. And an interrupt circuit for sending an interrupt signal for notifying the second CPU that the data of the second storage means has been read. Computer system.

According to another aspect of the invention, the interrupt circuit is configured to transmit the data transmitted from the first CPU by using a predetermined bit of the data bus, the status transmitted from the second CPU, and It is characterized in that it is controlled by the selection signal for the interrupt circuit and the read / write signal for the interrupt circuit to notify the corresponding to the first CPU or the second CPU.

Further, in the invention described in claim 4, the interrupt circuit comprises a first flip-flop and a second flip-flop, and the output of the first flip-flop is the first memory. The first flip-flop is cleared by the signal for notifying the reading of the data from the first storage means, and the output of the second flip-flop is the second signal. It is characterized in that it becomes a signal for notifying the reading of data from the storage means and that the clearing of the second flip-flop becomes a signal for notifying the writing of data to the second storage means.

[0012]

According to the invention described in claim 1, the first CPU
Includes a first storage unit for writing data and a second CPU for reading data, and a second storage unit for the second CPU to write data and the first CPU reads data. Since it is provided, it is possible to send and receive data bidirectionally using the respective storage means. Moreover, the interrupt circuit notifies the second CPU that data has been written to the first storage means, and also notifies the first CPU that data has been written to the second storage means. Since the CPU interrupt signal is transmitted, one of the CPUs can transmit and receive appropriate data without having command authority.

According to the second aspect of the present invention, the interrupt circuit notifies the first CPU that the data of the first storage means has been read, and the data of the second storage means. Since an interrupt signal for notifying the second CPU that the data has been read is transmitted, one of the CPUs can transmit and receive appropriate data without having command authority.

According to the third aspect of the present invention, the first CPU sends data by using a predetermined bit of the data bus, and the second CPU sends status to interrupt. The circuit can be controlled, and appropriate data can be transmitted and received without changing the conventional control.

Further, according to the invention described in claim 4, the interrupt circuit includes a first flip-flop and a second flip-flop, and by setting and clearing the first flip-flop, the first and second flip-flops are provided. The read / write notification of the data of the second storage means is appropriately performed, and the bidirectional data transmission / reception is efficiently performed.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A computer system according to an embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a configuration example of a computer system according to the embodiment. A first CPU 1 that exchanges data with a control unit that controls exchange, and a second CPU that exchanges data with a terminal.
The CPU 2 is connected to the storage device first storage means 3 and second storage means 4 which are constituted by, for example, a dual port RAM. In the first storage means 3, the first CPU 1
Writes data via the data bus 8-1, and the second CPU 2 reads data via the data bus 8-2. In the second storage unit 4, the second CPU 2 writes data via the data bus 8-2, and the first CPU 1 reads data via the data bus 8-1. First C
The PU 1 is connected to the second CPU 2 via the address assigner 5.
Accesses the first storage means 3 and the second storage means 4 via the address assigner 6, respectively. Output of address assigner 5, data on data bus 8-1, second C
The interrupt circuit 7 to which the interrupt request signal from PU2 is input is
First data is sent to the first CPU1 and the second CPU2.
An interrupt for notifying that the data has been written in the storage means 3 and the second storage means 4 is generated. Interrupt circuit 7
Makes it possible to notify the first CPU 1 that the data in the first storage means 3 has been read out by using 1 bit of the data bus 8-1, and that the data in the second storage means 4 has been read out. Is notified to the second CPU 2 using an interrupt signal.

FIG. 2 shows a block diagram of the interrupt circuit 7. The interrupt circuit 7 includes a flip-flop 11 for notifying that data has been written to the first storage means 3 and a flip-flop for notifying that data has been read from the second storage means 4. 12 are provided. When the signal SEL designating the interrupt circuit 7 output from the address assigner 5 and the write signal WR are at the L level, the flip-flops 11 and 12 respectively output the least significant bit of the data bus 8-1 and the next bit. The bit is fetched, sent to the second CPU 2 as an interrupt signal, and cleared by the status from the second CPU 2. The output of the flip-flop 11 is a signal SEL designating the interrupt circuit 7 of the address assigner 5.
When the read signal RD and the read signal RD are at the L level, they are read out to the least significant bit of the data bus 8-1 via the 3-state buffer 15. The NAND gate 13 is a gate for controlling the 3-state buffer 15, and the AND gate 14
Is a gate for supplying a clock to the flip-flops 11 and 12. The clear signal for the flip-flop 12 is given to the first CPU 1 as an interrupt signal for notifying that the data has been written in the second storage means 4.

The first CPU 1 and the second CPU 2 have a program for operating corresponding to the flow chart shown in FIG. 3, and by using this program, the data in the first storage means 3 is stored. The transmission / reception control will be described below. The first CPU 1 monitors whether or not data to be sent to the second CPU 2 has occurred (S31).
When data to be sent to the second CPU 2 occurs, the first
The CPU 1 outputs the address to the address assigner 5 so that the signal SEL designating the interrupt circuit 7 and the read signal RD become L level. Then Nand Gate 13
Sets its output to the L level, so that the 3-state buffer 15 enters the output state, inverts the output of the Q terminal of the flip-flop 11 and sends it to the least significant bit of the data bus 8-1. The first CPU 1 fetches the least significant bit (D0) and detects the air blockage of the first storage means 3 (S3).
2). That is, when the data is read from the first storage means 3, the second CPU 2 gives a clear signal to the flip-flop 11, so that the output of the Q terminal of the flip-flop 11 becomes L level. Therefore, when the least significant bit of the data bus 8-1 is at H level, the first storage means 3 is empty. When the first storage means 3 is empty,
The first CPU 1 writes the data to be sent to the second CPU 2 into the first storage means 3 (S33), and the signal SEL designating the interrupt circuit 7 for the address assigner 5 and the write signal WR are at L level. The address is output so that Then, the AND gate 14 sets its output to the H level, so that the clock is applied to the clock terminals ck of the flip-flops 11 and 12. At the same time, the first C
PU1 sends H level to the least significant bit of data bus 8-1 (the bit next to the least significant bit is L level).
As a result, the flip-flop 11 is set, the output of its Q terminal becomes H level, and the second CPU
An interrupt signal to the effect that data has been written to the first storage means 3 is given to 2 (S34). The second CPU 2 that has received the interrupt performs processing according to the priority of the interrupt, and
The data is read from the storage means 3 (S3
5). When the reading is completed, the second CPU 2 gives a clear signal to the flip-flop 11, so that the output of the Q terminal of the flip-flop 11 becomes L level, indicating that the first storage means 3 is empty (S36). .

The first CPU 1 and the second CPU 2 have a program for operating corresponding to the flow chart shown in FIG. 4, and by using this program, the data in the second storage means 4 is stored. The transmission / reception control will be described below. The second CPU 2 monitors whether data to be sent to the first CPU 1 has occurred (S41).
When the data to be sent to the first CPU 1 is generated, the second CPU 2 generates the flip-flop 1 via the interrupt input terminal.
The output of the Q terminal of No. 2 is fetched and the air blockage of the second storage unit 4 is detected (S42). That is, the first CPU sets the flip-flop 12 to the set state when the data is read from the second storage means 4, so that the output of the Q terminal is H.
It becomes a level. Therefore, when the signal level of the signal line 23 is H level, the second storage means 4 is empty. When the second storage means 4 is empty, the second CPU 2 writes the data to be sent to the first CPU 1 into the second storage means 4 (S43), and the flip-flop 1
The status (L level) for clearing 2 is transmitted via the signal line 25. This status is configured to be sent to the interrupt input terminal of the first CPU 1 via the signal line 21, and the interrupt signal indicating that the data has been written in the second storage means 4 is sent to the first CPU 1. Is given (S44).
The first CPU 1 that has received the interrupt performs processing according to the priority of the interrupt and reads the data from the second storage unit 4 (S45). When reading is completed, the first
The CPU 1 outputs the address to the address assigner 5 so that the signal SEL designating the interrupt circuit 7 and the write signal WR become L level. Then, AND gate 1
4 sets its output to the H level, so that the clock is applied to the clock terminals ck of the flip-flops 11 and 12. At this time, the first CPU 1 simultaneously operates the data bus 8-
The H level is sent to the bit (D1) next to the least significant bit of 1 (the least significant bit is the L level). As a result, the flip-flop 12 is set, the output of the Q terminal thereof becomes H level, and the fact that the data of the second storage means 4 has been read out to the second CPU 2 (the second storage means 2 is empty). To the effect (S46).

Thus, the first CPU 1 and the second CPU 2
In other words, it becomes possible to simultaneously send and receive data having different directions by using different storage means 3 and 4, respectively. Moreover, since they interrupt each other, compared to the case where one side has the command authority, it is possible to read the data by interrupting and prepare for the next data transmission (storage). Less likely to disappear. Also, the first CP
As before, except for U1 being interrupted, the first C
The PU1 controls the interrupt circuit 7 using the data bus,
The CPU 2 is configured to control the interrupt circuit 7 using the status, and it is possible to send and receive appropriate data without significantly changing the control.

[0021]

As described above, according to the present invention, data can be transmitted and received bidirectionally using the storage means. Further, in the invention of claim 1, the interrupt circuit notifies the second CPU that the data has been written in the first storage means, and the data writing in the second storage means is notified. Since the interrupt signal for notifying to one CPU is sent out, it is possible to send and receive appropriate data without one CPU having command authority.

According to the second aspect of the invention, since the reading is mutually notified, the writing to the storage means can be appropriately performed, and one CPU does not have the command authority. Enables sending and receiving of appropriate data.

According to the invention of claim 3, the first CPU uses a predetermined bit of the data bus,
Since the second CPU controls the interrupt circuit by sending the status, it is possible to send and receive appropriate data without significantly changing the conventional control.

Further, according to the invention described in claim 4, the interrupt circuit comprises a first flip-flop and a second flip-flop. By setting and clearing the first flip-flop, the first and second flip-flops are provided. The read / write notification of the data of the second storage means is appropriately performed, and the bidirectional data transmission / reception is efficiently performed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a computer system according to an embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of a main part of a computer system according to an embodiment of the present invention.

FIG. 3 is a flowchart for explaining the operation of the computer system according to the embodiment of the present invention.

FIG. 4 is a flowchart for explaining the operation of the computer system according to the embodiment of the present invention.

FIG. 5 is a configuration diagram of a computer system according to a conventional example.

FIG. 6 is a flowchart for explaining the operation of a computer system according to a conventional example.

[Explanation of symbols]

1 First CPU 2 Second C
PU 3 First storage means 4 Second storage means 5, 6 Address assigner 7 Interrupt circuit 8-1, 8-2 Data bus 11, 12
Flip-flop 13 NAND gate 14 AND gate 15 3-state buffer

Claims (4)

[Claims] 1. A first CPU and a second CPU are provided,
In a computer system in which these CPUs exchange data with each other, the first CPU writes data and the second CP
U is a first storage unit for reading data, the second CPU writes data, the first CP
U notifies the second CPU that the U has read the data, the second CPU that the U has written the data, and that the U has written the data to the second storage. An interrupt circuit that sends an interrupt signal for notifying the first CPU. 2. A first CPU and a second CPU are provided,
In a computer system in which these CPUs exchange data with each other, the first CPU writes data and the second CP
U is a first storage unit for reading data, the second CPU writes data, the first CP
U notifies the first CPU that the second storage means for reading data and the data of the first storage means has been read, and that the data of the second storage means has been read. A computer system, comprising: an interrupt circuit for sending an interrupt signal for notifying the second CPU. 3. The interrupt circuit includes data sent from the first CPU using a predetermined bit of the data bus and a second C.
Controlled by a status sent from the PU, a selection signal for the interrupt circuit, and a read / write signal for the interrupt circuit, the corresponding notification is sent to the first CPU or the second CPU. Computer system to do. 4. The interrupt circuit comprises a first flip-flop and a second flip-flop, the output of the first flip-flop being a signal notifying the writing of data to the first storage means, The first flip-flop is cleared by the signal of the data read notification from the first storage means, and the output of the second flip-flop becomes the signal of the data read notification from the second storage means. A computer system characterized in that the clearing of the second flip-flop is a signal notifying the writing of data into the second storage means.