JPS6227846A - Input and output channel - Google Patents

Abstract

PURPOSE:To increase the number of terminals which can be processed at a time by improving the character processing capacity of an input/output channel. CONSTITUTION:A DMA control circuit 15 which transfers the data stored temporarily in an input/output buffer 13 and delivered through a terminal to a main storage is provided to an input/output channel 10 together with a memory means 44. The interruption request data is set previously by a setting means at the address position of a memory means 44 which is designated by an address consisting of at least a special character. The means 44 receives a read access from an address containing the data read out of the buffer 13 in a DMA transfer period under the control of the circuit 15. If the data read out of the memory means 44 is equal to the interruption request data, an interruption is produced by an interruption indicating means to a microprocessor 11. At the same time, the interruption is indicated for the DMA request of the circuit 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an input/output channel that processes multiple terminals simultaneously, and particularly to its character processing method.

[Technical background of the invention]

Generally, when this type of input/output channel receives a data input request from the CPU, it checks all input data to see if there are any special characters such as delimiter characters in the data input from the terminal. and judge. After this determination, the input/output channel executes data transfer (data input/output) to the main memory according to the number of data input requested words.

[Problems with Background Art] The above-described checking of all input data is performed by the microprocessor of the input/output channel.

Therefore, the input data processing capability of the entire input/output channel is limited primarily by the character processing capability of the microprocessor. That is, the conventional input/output channel is
The drawback was that the input data processing capacity was lower than the output data processing capacity.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and its object is to provide an input/output channel that can improve character processing ability and thereby improve input data processing ability.

[Summary of the Invention] According to the present invention, an input/output channel incorporating a microprocessor and controlling input/output between a plurality of terminals and a main memory is provided. This input/output channel allows data from the terminal that is temporarily stored in the input/output buffer to be transferred to the main memory.
A DMA1blJ control circuit for MA transfer and memory means are provided. At an address location of this memory means specified by an address consisting of at least special characters,
Interruption request data instructing DMA interruption is set in advance by the setting means. The memory means is read accessed by an address containing data read from the input/output buffer during a DMA transfer period under control of the DMA control circuit. If the data read from the memory means is interrupt request data, the interrupt instruction means generates an interrupt to the microprocessor and instructs the DMA request of the DMA i,+ control circuit to be interrupted.

[Embodiment of the Invention] FIG. 1(a) shows the configuration of an input/output channel 10 according to an embodiment of the invention.

The input/output channel 10 may be connected to a plurality of terminals (not shown), for example.
It is a multi-terminal control input/output channel that simultaneously processes data, and is connected to the CPU and main memory (both not shown) via the system bus 30. A microprocessor 11, which controls the entire input/output channel 10, is connected to an internal bus 12.

Connected to the internal bus 12 are an input/output buffer 713 having a RAM configuration that temporarily stores output data from a main memory (not shown) to the terminal and input data from the terminal to the main memory, and a special character detection section 14. ing. This special character detection section 14 detects a preset special character from the data read from the input/output buffer 13, and performs input/output control between the crowd buffer 13 and the main memory. -3DMAilJ1 time M (DMAC1)
It is also connected to 15. Also connected to the internal bus 12 are a plurality of interface circuits (1/F) 16 that form interfaces with each terminal. Each interface circuit 16 has a DMA III circuit that performs input/output control between the interface circuit 16 and the input/output buffer 13.
m circuit ([) MAC2>17tC connected, D tvI
A1Ill in circuit 17 is microprocessor 1
Connected to 1.

Now, the input data that is inputted from the terminal without any procedure is first sent to the corresponding interface circuit 16. under the control of the DMA illm circuit 17. It is temporarily stored in the input/output buffer 13 via the internal bus 12.

Eventually, the microprocessor 1 in the input/output channel 10
1 accepts a data input request (to the main memory) from the CPU transferred via the system bus 30 (this route is not shown because it is not directly related to this invention), and receives a desired special character ( A special character registration process is performed in which a special character (not limited to one character) is registered in the special character detection unit 14.

After completing the special character registration process, the microprocessor 11 instructs the D M Aυ 1111 circuit 15 to transfer the input data from the terminal temporarily stored in the input/output buffer 13 to the main memory (via the system bus 30). Instruct. As a result, the D M A Ill m circuit 15
executes DMA transfer from the input/output buffer 13 to the main memory. In this DMA transfer, is there an input/output buffer? 1
Read data from 3 is directed to internal bus 12. The input of a register (REG) 18 is connected to the internal bus 12, and the output of the register 18 is connected to a system bus 30. The register 18 is controlled by a bus 1 fault circuit 19 connected to the register 18. Bus control circuit 19
DM A III! 11 circuit 15 and a system bus 30, and acquires the system bus 30 in response to a DMA request from the DMA control circuit 15 (requesting DMA transfer from the input/output buffer 13 to the main memory), and transfers the system bus 30 to the internal bus. The operation of setting the data on the register 12 in the register 18 and outputting it to the system bus 30 is repeatedly executed. In this embodiment, the data width of internal bus 12 is 1 byte, and the data width of system bus 30 and register 18 is 4 bytes. Therefore, the bus control circuit 19 transfers the contents of the register 18 to the system bus 3 every time 4 bytes of read data from the input/output buffer 13 is set in the register 18.
It is designed to output to 0.

The data on the internal bus 12 (ie, the data read from the input/output buffer 13 and transferred to the main memory) is also guided to the special character detection section 14. The special character detection unit 14 has a special character detection function that detects special characters (for example, delimiter characters, etc.) registered in the special character registration process from the data transferred to the main memory. When the special character detector 14 detects the registered special character lid, it generates a DMA interrupt request and an interrupt request.

The special character detection section 14 is connected to an interrupt III al1 circuit 21 via an interrupt request circuit 20, and the open interrupt control circuit 21 is connected to the microprocessor 11. Therefore, the interrupt request from the special character detection unit 14 is transmitted to the interrupt IHI 11 circuit 21 via the interrupt request circuit 20, and
The microprocessor 11 is notified under the control of the microprocessor 11. As a result, the microprocessor 11 performs the illustrated interrupt processing and ends its operation. Further, a DMA interrupt request from the special character detection section 14 is transmitted to the bus control circuit 19 via the DMA control circuit 15, thereby interrupting the DMA transfer.

Next, mainly the special character detection section 1 shown in FIG. 1(a).
The configuration and operation of 4 will be explained in detail with reference to FIG. 1(b).

The special character detection unit 14 includes a register (REGI) connected to the internal bus 12, as shown in FIG. 1(b).
4t, a register (REG2>42) is provided.

In the special character registration process, the microprocessor 11 sends a desired special character to the internal bus 12 and outputs an active latch signal H. This signal H is supplied to the register 41 via a signal line (not shown). As a result, the special character on the internal bus 12 is set in the register 41.

The output of the register 41 is a selector (SEL) with two inputs and one output.
) 43, and the other input of the selector 43 is connected to the internal bus 12.

A DMA request signal J from the DMA control circuit 151fi (which requests DMA transfer from the input/output buffer 13 to the main memory) is guided to the selector 43 as a selection control signal. When the signal J is inactive, the selector 43 selects
If the MA control circuit 15 is not in the DMA request state, it selects the contents of the register 41 (in this example, a special character).

When the microprocessor 11 sets the special character in the register 41, it sends a value indicating the input/output boat to which the data input source terminal is connected (input/output boat number) to the internal bus 12, and also outputs the active latch signal K.
Output. This signal is supplied to the register 42 via a signal line (not shown).

As a result, the input/output port number on the internal bus 12 is set in the register 42.

The outputs of the register 42 and the selector 43 are connected to an address input terminal A of a memory means, for example a RAM 44. Thus, the contents of the register 42 (in this example, the input/output port number) and the selected output data from the selector 43 (in this example, the special character) are concatenated and stored in the RAM 44.
is supplied to address input terminal A of . Here, the contents of the register 42 indicate the upper address for the RAM 44,
Selected output data from the selector 43 similarly indicates the lower address. The data input/output end of the RAM 44 is connected to one input/output end of a bidirectional transceiver (XCVR) 45, and the other input/output end of the transceiver 45 is connected to the internal bus 1.
Connected to 2.

When the microprocessor 11 sets the input/output capo number in the register 42, the microprocessor 11 sends the special character condition data used for the DMA interrupt request bit onto the internal bus 12. At this time, microprocessor 1
1 outputs an active signal that enables the transceiver 45, and also outputs a signal M that specifies the input/output direction of the transceiver 45. Here, signal M specifies the output of data on internal bus 12 to RAM 44. The signals M and M are supplied to the transceiver 45 via a signal line (not shown). This allows transceiver 4
5 outputs the data (here, special character condition data) on the internal bus 12 to the data input/output end of the RAM 44.

Furthermore, the microprocessor 11 outputs a write signal N specifying writing to the RAM 44. This signal N is supplied to the write end WR of the RAM 44 via a signal line (not shown). As a result, the RAM 44 is set to write mode, and the RAM 44 is designated by the concatenated data of the contents of the register 42 and the selected output data of the selector 43 (in this case, the concatenated data of the input/output boat number and the special character).
Special character condition data is written to the address. The above is the special character registration process. This process is
Repeated for the number of special characters that need to be registered.

When the microprocessor 11 completes the special character registration process, it instructs the DMA control circuit 15 to transfer the data from the terminal temporarily stored in the input/output buffer 13 as described above to the main memory. This allows the DMA
The control circuit 15 controls the D output from the input/output buffer 13 to the main memory.
Execute MA transfer. In this DMA transfer, DM
An active MA request signal J is generated from the A control circuit 15. As a result, the selector 43 selects the internal bus 1 from among the contents of the register 41 and the data on the internal bus 12.
2 is selected as the lower address of the address for the RAM 44. Therefore, during the DMA transfer period,
The address of the RAM 44 is determined by the concatenated data of the input/output boat number (the contents of the register 42) and the read data from the input/output buffer 13 (that is, the data transferred to the main memory) (the data on the internal bus 12). It is specified.

The output of the OR gate 46 is connected to the read end RD of the RAM 44 . The read signal P and the above-mentioned DMA request signal J are led to the input of the OR gate 46 via a signal line (not shown).

The signal P is output from the microprocessor 11 when the microprocessor 11 reads data stored in the RAM 44. Therefore, during the DMA transfer period,
DM A! The active signal J from the II control circuit 15 is sent to the RAM via the OR gate 46 as a read signal.
44 to the read end RD. This allows RAM4
4 is set to read mode, and the data at the address of the RAM 44 specified by the concatenated data of the input/output boat number and the data read from the input/output buffer 13 (data transferred to the main memory) is read from the data input/output end. Read out.

The first bit at the data input/output end of RAM 44 is AN.
It is connected to one input of the D gate 47, and the AND gate 4
The other input of 7 is connected to the above-mentioned DMA request signal J. Thus, the first bit of data read from RAM 44 is supplied to AND gate 47. AND gate 4
7 is during the period when the signal J is active, that is, the D to the main memory is
During the MA transfer period, the first bit of the read data from the RAM 44 is output as is. The output of the AND gate 47 is connected to the S input of a flip-flop 48 of the RS type, for example. A reset signal Q from the microprocessor 11 is connected to the R input of the flip-flop 48.

When the output of the AND gate 47 is active, that is, during the DMA transfer period, the flip-flop 48 controls the RAM 4
Set if the first bit of data read from No. 4 is active. The first bit is active (RAM
The read data (from 44) is special character condition data whose first bit is used as the DMA interrupt request bit, as described above.

This special character condition data is read from the RAM 44 when the data read from the input/output buffer 13 that specifies the lower address of the RAM 44 during the DMA transfer period is a special character characterized by DMA transfer interruption. The buffer 48 is configured such that the read data from the input/output buffer 13 is (D) during the DMA transfer period.
Set when a special character is characterized by MA transfer interruption, indicating that a special character has been detected.

The d output of the flip 70 tube 48 is connected to one input of an AND gate 49, and the other input of the AND gate 49 is connected to the DMA request signal J.

The output signal of the AND gate 49 is guided to the bus control circuit 19 as a DMA request signal R to the bus control circuit 19 via the DMA III control circuit 15. As is clear, when flip 70 knob 48 is set, AND
The DMA request signal R from the gate 49 is DMA II.
Active from I control circuit 15 M A request signal @J
becomes inactive regardless of In this case, the DMA transfer is interrupted as described above. On the other hand, the Q output of the flip 70 tube 48 is used as a signal S for requesting an interrupt to the microprocessor 11. This signal S is led to the interrupt request circuit 20 via a signal line (not shown). When the flip 70 knob 48 is set and the signal S becomes active, a vj interrupt is applied to the microprocessor 11 via the interrupt request circuit 201 and the interrupt control circuit 21.

When the microprocessor 11 receives an interrupt from the interrupt control circuit 21 by setting the flip-flop 48, the microprocessor 11 performs interrupt processing. In this interrupt processing, the microprocessor 11 checks specific bits other than the first bit of the special character condition data read from the RAM 44, for example. This specific bit is designed to specify whether or not the corresponding special character should be transferred to the main memory. If the detected special character is a character that needs to be transferred to the main memory, the microprocessor 11 replaces all (valid) data set in the register 18 with a character that does not need to be transferred to the main memory. If so, the data preceding the special character at the bottom of all the data set in the register 18 is output to the system bus 30. And the microprocessor 11 is
The data output to the system bus 30 is written to the main memory and the operation is completed.

As described above, according to this embodiment, whether the input data from the terminal includes a predetermined special character or not is determined by the microprocessor in parallel with the DMA transfer from the input/output buffer 13 to the main memory. Furthermore, by detecting the special character, it is possible to interrupt the DMA transfer and interrupt the microprocessor 11 at the same time.

That is, according to this embodiment, character processing can be performed correctly without the microprocessor 11 checking the input data from the terminal temporarily stored in the input/output buffer 13 in advance as in the conventional case.

Now, when the microprocessor 11 receives a data input request (to the main memory) from the CPU again after completing the above-described interrupt processing, it supplies an active reset signal Q to the R input of the flip-flop 48 and Reset the knob 48. As a result, the suspended state of the DMA transfer is released and the DMA transfer is restarted.

Note that the DMA request signal R from the AND gate 49 may be directly supplied to the bus control circuit 19.

Further, even if the AND gate 49 is provided in the DMA III circuit 15, there is no problem.

[Effects of the Invention] As described in detail above, according to the present invention, the character processing ability in the input/output channel can be improved, so that the input data processing ability can be improved. Therefore, the number of terminals that can be processed simultaneously can be increased.

[Brief explanation of the drawing]

FIG. 1(a) is a block diagram of an input/output channel according to an embodiment of the present invention, and FIG. 1(b) is a block diagram showing the internal configuration of the special character detection section 14 shown in FIG. 1(a). It is. DESCRIPTION OF SYMBOLS 10... Input/output channel, 11... Microprocessor, 13... Input/output buffer 7.14... Special character detection section, 15... DM A ill 'm1
Circuit (DMAC1), 19... bus control circuit, 44.
...RAM, 48...Flip-flop. Applicant's agent Patent attorney Takeshi Hikomoto
eyes (a) narrow eyes (b)

Claims (3)

[Claims] (1) In an input/output channel that has a built-in microprocessor and can be connected to multiple terminals, there is a DMA control circuit that transfers data from the terminal temporarily stored in the input/output buffer to the main memory by DMA; D by control
Instructing a DMA interruption to a memory means read accessed by an address containing data read from the input/output buffer during the MA transfer period, and to an address location of the memory means specified by an address consisting of at least special characters. a setting means for presetting interrupt request data; and an interrupt instruction for generating an interrupt to the microprocessor when the interrupt request data is read from the memory means and for instructing interrupt of the DMA request from the DMA control circuit. An input/output channel comprising means. (2) The input/output channel according to claim 1, wherein the address for the memory means includes terminal identification information. (3) The above-mentioned interruption instruction means is D indicated by the above-mentioned interruption request data.
3. The input/output channel according to claim 1, wherein the input/output channel is a flip-flop that stores an MA interrupt request.