KR940003845B1 - Communication path bus selecting method - Google Patents

Abstract

The processor employing the method improves the reliability of error process and speeds up the process. The method employs a low level main board (1), a low level interface boards (2,8) which comprises GPIP and DDR, a hardware units(12 or 15) which connect low level interface board to TD-bus(6). The method includes a lst step (102) which selects one of hardware units (15 or 17) via a parameter, a 2nd step (104) which reads or writes a registor of GPIR and assigns GPIR to hardware port address (103), a 3rd step which assigns DDR to hardware signal and data input-output direction, and a 4th step which selects a bus through bits 4,7.

Description

How to Select Monetary Bus for Lower Level Processors

1 is a hardware diagram for implementing the present invention.

2 is a flow chart showing the implementation of the present invention.

* Explanation of symbols for main parts of the drawings

1: Lower level main board 2, 8: Interface board

3, 9: MFP 4, 10: Memory

5, 11: Control registers 6, 7: TD-bus

12 to 15 hardware unit 16: device

100: PPA 200: PPB

The present invention relates to a bus route bus selection method of a lower level processor (hereinafter, referred to as a PP) of an electronic switching system.

In general, a monetary system bus (hereinafter referred to as a TD bus) is an information exchange path between a PP and a hardware unit, and various types of hardware units may be connected to the PP. TD-bus selection is also one of the ways in which a user program can indirectly access a hardware unit through a lower-level operating system by providing consistent TD-bus control. Conventionally, the user program performs all the functions of the hardware unit, so the error is not perfect, and there is no compatibility and unity with the device.

Therefore, an object of the present invention is a call processing function, maintenance function in the electronic exchanger. The hardware unit test function is to implement the TD-bus selection method so that all functions can be performed by the hardware unit.

The present invention provides a multi-function peripheral processor (MFP) 3 which is connected to a lower level main board, the lower level main board, and has a general purpose interrupt register (GPIP) and a data direction register (DDR) to achieve the above object. Low-level interface board, including a hardware unit connected to the lower-level interface board by a TD-bus, and selected by the TD-bus duplication path bus of the electronic switchboard centered around the hardware unit A method, comprising: a first step of receiving a parameter from a user program in a reception standby state and selecting one of the hardware units, assigning the GPIP to a hardware port address, and then reading and writing a register value of the GPIP; The third step of designating the input / output direction of hardware signals and data to DDR, the hardware of the GPIP The fourth step is to select a bus using bits 4 and 7 to monitor the signal.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a hardware diagram for the implementation of the present invention.

In the figure, 1 is a lower-level motherboard, 2 and 8 are interface boards, 3 and 9 are Multi-Function Peripheral Processors (MFPs), 4 and 10 are memory, 5 and 11 are control registers, 6 and 7 represents a TD-bus, 12-15 represents a hardware unit, 16 represents a device, 100 represents the A side of PP, and 200 represents the B side of PP.

The hardware environment for the implementation of the present invention comprises a lower level main board 1, an interface board 2 and 8 connected to the lower level main board 1, and a TD bus 16 to the interface board 2, respectively. Hardware units 12 and 13 connected to each other and having a plurality of devices 16 built therein, and hardware units connected to the interface board 8 by a TD bus 6 and each having a plurality of devices 16 embedded therein. It is composed of (14, 15) and is duplicated into PPA (100) and PPB (200) by TD-buses (6, 7). In addition, the interface boards 2 and 8 are connected to the memory 4 and 10 for storing and transmitting the actual data and to the memory 4 and 10 so that information exchange between the PP and the hardware units 12 to 15 can be performed. MFP (3,9), which is a chip for the purpose, is connected to the MFP (3,9) and consists of a control register (5, 11) for controlling hardware signals

The TD-buses 6 and 7 consist of an A-bus 6 and a B-bus 7 which are the actual buses connected to the processor located at the PPA 100 in the redundant PP, B-bus 7 is the actual bus connected to the processor located in PPB 200. Therefore, the PPA 100 can access the hardware units 12 to 15 only through the A-bus 6 and the PPB 200 through the B-bus only. The hardware units 12 to 15 are also classified according to the port address in the lower level main board 1. Therefore, when the user provides two parameters to the lower level operating system, the PP 100,200 receives this parameter and selects one of the TD-buses 6 and 7 or the lower level units 12 to 15 from the lower level operating system.

2 is a flow chart showing the implementation of the present invention.

When parameters 1 and 2 are received from the user program (101), one of four hardware units (12 to 15) is selected (102), and the GPIP (General Purpose Interrupt Register) in the MFP (3, 9) chip is not shown in the figure. To the hardware port address in the hardware motherboard 1 (103). After reading the register value of GPIP, write GPIP value once more (104) and input / output direction of hardware signal and data by specifying the value of DDR (Data Direction Register: not shown) in MFP (3,9) chip. (105). Finally, bit 7 of the GPIP monitors the TD bus selection signal of the other PP, and bit 4 monitors its own TD bus selection signal, so these two bits are used to select the bus. The bus selection method selects the B-bus 7 when the two bit states are the same, i.e., 0, 0 or 1, 1 (106, 107, 108), and when the two bits are different, i.e. when it is 0, 1 or 1, 0, 6) (106,107,109). Then, the transition to the data transmission standby state in the next TD-bus communication (110).

The effect by the present invention is as follows.

Firstly, the reliability of error handling increases when an error occurs during the execution of TD-bus communication.

Second, by providing a common procedure in the operating system, it provides the convenience of the user program and unifies the TD-bus communication program.

Thirdly, speed is improved through the high-speed bus.

Claims (2)

A lower level motherboard (1), which is connected to the lower level motherboard (1) and comprises a Multi-Function Peripheral Processor (MFP) (3) having a General Purpose Interrupt Register (GPIP) and a Data Direction Register (DDR) A lower level interface board (2,8), a hardware unit (12 to 15) connected to the lower level interface board (2,8) by a TD bus (6) and by the TD bus (6,7) In the method of selecting a telephone system bus of an all-electronic switching center which is duplicated around the hardware units 12 to 15, one of the hardware units 12 to 15 receives a parameter from a user program in a reception standby state 101. In the first step of selecting (102), assigning the GPIP to the hardware port address (103), and reading and writing the register value of the GPIP (104), the second step, and input / output directions of hardware signals and data to the DDR Third to specify System, system bus selection method in the currency of the lower level processors, characterized by consisting of a fourth step of selecting a bus with the bit 4 and 7 that monitors the hardware of the signal GPIP. The first process of claim 1, wherein the fourth step analyzes the states of bits 4 and 7 of the GPIP and selects the B-bus 7 if they match (108). 8) a second process of selecting and a third process of waiting for data transmission after the bus selection.