JPH1091302A - Setting data informing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the setting data informing circuit which can reduce the number of signal lines. SOLUTION: The circuit which informs a control part 13, performing specific operation, bit by bit, according to setting data consisting of plural bits, of pieces of setting data from a CPU 11 is provided with a memory 14 with specific-bit width which have data storage areas where the CPU 11 can write the setting data and the control part 13 can read them. Then the CPU 11 outputs indication signals (setting data read indication signal lines 15a and 15b) by the setting data to the control part 13, which reads the contents of the memory 14 by the setting data according to the indication signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control unit for performing a predetermined operation for each bit in accordance with setting data composed of a plurality of bits, such as a LAN connection device having a plurality of communication ports. The present invention relates to a setting data notification circuit that notifies a plurality of setting data, and more particularly to a setting data notification circuit that can reduce the number of signal lines.

[0002]

2. Description of the Related Art FIG. 8 shows an apparatus having a plurality of communication ports. This device has a terminal 8 on each port.
1 is connected, and communication between terminals via this device can be realized. As a device for connecting such a plurality of terminals, there is a switching hub. Since the switching hub reads the destination of the frame and transfers the frame only to the corresponding port, communication between a plurality of sets of terminals can be realized, and the speed of the network can be easily increased.

In a switching hub, a virtual LA
A feature called N has recently attracted attention. The virtual LAN is a function for grouping ports. In order to implement a virtual LAN, it is necessary to perform separate transmission / reception processing for each port, and for this purpose, processing must be set for each port.

FIG. 9 is a diagram showing a register for storing processing settings for each port. In the setting data stored in this register, one bit corresponds to one port, and whether or not one process is performed is indicated by the bits “1” and “0”. If the number of ports is 32 as in the device of FIG. 8, the number of bits of the setting data is also 32, and the bit width of the register is also 32 from b0 to b31.

[0005] As an example of processing set for each port,
For example, transmission / reception frames of a certain port always have specific header information attached thereto, and received frames from a certain port do not perform automatic address learning. The writing of the setting data to the register is performed by the CPU in the apparatus according to a command from the network management station or the like. The setting data of this register must be notified to the communication control unit.

FIG. 10 is a diagram showing a conventional setting data notification circuit. A CPU control unit 12 is connected to the CPU 11, and two notification signal lines 91 a and 91 b are provided from the CPU control unit 12 to the communication control unit 13. 32 notification signal lines 91a and 91b are provided respectively.
The register having the bit width of 32 described in FIG. 9 is provided in the CPU control unit 12. This register is
1 can be read / written, and the contents are notified to the communication control unit 13 via the notification signal lines 91a and 91b. Setting data indicating whether to perform one process A is output to the notification signal line 91a, and setting data indicating whether to perform another process B is output to the notification signal line 91b.
The communication control unit 13 transmits these notification signal lines 91a, 91b
The transmission and reception process in each port is performed according to the setting data from.

[0007]

[0010] In the example of FIG.
Notification signal line 91 from U control unit 12 to communication control unit 13
32 × 2 = 64 signal lines are required as a and 91b. When the number of processes A, B,... Increases, the number of registers also increases. When the number of registers reaches K, 32 ×
K signal lines are required.

The CPU controller 12 and the communication controller 13 are realized by a dedicated LSI such as a gate array.
If the CPU control unit 12 and the communication control unit 13 can be realized by the same LSI, there is no problem even if there are many signal lines between the CPU control unit 12 and the communication control unit 13 in the LSI. However, due to restrictions due to the hardware configuration of the entire switching hub and restrictions on the maximum number of pins of the LSI, C
When the PU control unit 12 and the communication control unit 13 are realized by different LSIs, the following problem occurs.

First, in each LSI, 32 ×
Since K connection pins are required, more pins LS
It is necessary to use I or to further divide the LSI, which causes a problem that the cost of the LSI increases. A larger board for mounting the LSI is also required, which leads to an increase in cost.

In addition to the above problems, the LS for the CPU control unit
When the board on which the I and the communication control unit LSI are mounted is separated, the number of signal lines for connection between the boards increases, the amount of the entire hardware increases, and the cost increases.

An object of the present invention is to provide a setting data notification circuit which can solve the above-mentioned problems and can reduce the number of signal lines.

[0012]

In order to achieve the above object, the present invention provides a control unit which performs a predetermined operation for each bit according to setting data composed of a plurality of bits.
In a circuit for notifying a plurality of setting data from U, a memory having a predetermined bit width having a plurality of data storage areas between which the CPU writes the setting data and the control unit can read is provided between the CPU and the control unit. Provided, the CPU
Outputs an instruction signal for each setting data to the control unit, and the control unit reads the contents of the memory for each setting data based on the instruction signal.

The bit width of the memory is M / N with respect to the bit number M of one set data, the CPU writes one set data in N pieces, and the control section divides one set data in N times. The setting data may be read.

The instruction signal is a binary level signal,
When the level of the instruction signal changes from one level to the other level, the setting data is instructed, and the execution of the setting data is indicated according to the level. And the operation may be performed only when the level is executable.

[0015]

An embodiment of the present invention will be described below in detail with reference to the accompanying drawings.

As shown in FIG. 1, in the setting data notification circuit of the present invention, a CPU control unit 12 is connected to a CPU 11, and a notification memory 14 is provided between the CPU control unit 12 and the communication control unit 13. Have been. A 32-bit bidirectional signal line 16 is provided between the CPU control unit 12 and the notification memory 14.
And the CPU 11 can read / write the notification memory 14 via the CPU control unit 12. The notification memory 14 and the communication control unit 13 are connected by a 32-bit unidirectional signal line 17 so that the communication control unit 13 can read the notification memory 14.
The CPU control unit 12 and the communication control unit 13 are connected by setting data read instruction signal lines 15a and 15b.
As in the case of FIG. 10, two registers having a bit width of 32 are provided in the CPU control unit 12 for storing the setting data of the processes A and B. One set data read instruction signal line 15a, 15b is provided for each register.

As shown in FIG. 2, the communication control unit 13
Is an instruction signal input section 21 which receives setting data read instruction signal lines 15a and 15b as inputs and outputs a memory address signal and a memory control signal such as a memory read signal to the notification memory 14, and a 32-bit unidirectional signal. Line 17
, And a control unit main body 23 that performs a predetermined operation according to the setting data of the setting data latch units 22a and 22b.

FIG. 3 shows a storage area of each setting data in the notification memory 14. As shown, the notification memory 1
Reference numeral 4 designates a predetermined area for storing individual setting data. In this embodiment, the setting data “22a setting data” of the processing A and the setting data “22b setting data” of the processing B are stored in the respective areas 3.
1, 32.

Next, the operation of the setting data notification circuit of the present invention will be described.

FIG. 4 shows the timing when setting data is read. The CPU 11 stores “22a setting data” in a predetermined area in the notification memory 14, and switches the instruction signal of the setting data read instruction signal line 15a from OFF to ON. Note that the instruction signal can have two levels, upper and lower. In FIG. 3, the upper level is ON and the lower level is O.
FF. The instruction signal input unit 21 outputs the instruction signal
The rising edge 41 at which the FF is switched to ON is detected, and at that timing, the area storing the “22a setting data” in the notification memory 14 is read with a memory address signal indicating the address 42 and an active state memory read (Read). The read data (memory data) accessed by the signal 43 is latched by the setting data latch unit 22a at the latch timing. Thereafter, the control unit main body 23 performs a predetermined operation according to the setting data latched by the setting data latch unit 22a.

In FIG. 1, the number of signal lines between the CPU control unit 12 and the communication control unit 13 is 32 (memory data bus; bidirectional signal line and one-way signal line) +2 including that for the notification memory 14. To 4 (memory control signals such as a memory address signal and a memory read signal; different depending on the memory control method) +2 (setting data read instruction signal) = 36
~ 38. In the prior art shown in FIG. 10, 32 × 2 = 64 lines are required for processes A and B, so that the number of signal lines is considerably reduced. Here, the bit width of the memory is set to 3
2 bits, the number of registers (the number of processes A, B, ...) is K
In this case, the number of signal lines required for the present invention is 32 + K
(Instruction signal) +1 to 3 (memory control signal) + log ₂ K
(Memory address signal). If K ≧ 2, it is smaller than 32 × K lines of the prior art. The effect increases as K increases.

Next, another embodiment will be described. In the embodiments described above, the number of bits of the setting data and the bit width of the memory are the same, ie, 32 bits. It can be divided into In this case, the time for writing / reading to the memory increases,
Since the bit width of the memory data bus is reduced, the number of signal lines can be further reduced.

FIG. 5 shows that the bit width of the notification memory 14 is 8
This shows the storage area for each setting data. As shown in the figure, the notification memory 14 is assigned a predetermined 8-bit × 4 area for storing 32-bit setting data. That is, area 5 of “22a setting data”
1, setting data can be stored at consecutive addresses (1) to (4) in an area 52 of “22b setting data”.

FIG. 6 shows the timing when setting data is read. The CPU 11 stores “22a setting data” in a predetermined area in the notification memory 14, and switches the instruction signal of the setting data read instruction signal line 15a from OFF to ON. The instruction signal input unit 21 of the communication control unit 13 detects the rising 61 at which the instruction signal switches from OFF to ON.
Is detected, and “2” in the notification memory 14 is detected at that timing.
The area storing the “2a setting data” is successively accessed four times by a memory address signal in which the lower address of the address 62 is sequentially increased by +1 and a memory read (Read) signal 63 in an active state during the period. , And sequentially latches the read 32-bit data in the setting data latch unit 22a at four latch timings 64.

In this case, the number of signal lines is 8 (memory data bus) +4 to 6 (memory address signal, memory control signal) +2 (instruction signal) = 14 to 16 lines. As described above, the notification memory 1 corresponds to the bit number M of one setting data.
If the bit width of 4 is M / N, the CPU 11 writes one set of data in N pieces, and the communication control unit 13 reads one piece of set data in N times, the number of signal lines becomes It can be further reduced.

Next, another embodiment will be described. In the embodiments described above, the setting data read instruction signal is used only for reading the setting data. However, this signal is also used as an enable signal indicating whether or not to perform the entire process. In addition to the setting data indicating whether or not to perform the process A for each port as shown in FIG. 9, information indicating whether or not to perform the process A as a whole may be required. In this case, an enable signal is used.

As shown in FIG. 7, in the setting data notification circuit, in addition to the configuration shown in FIG. 2, setting data read instruction signal lines 15a and 15b are also connected to the control unit main body 23. The control unit main body 23 performs a corresponding process only when the instruction signals of these setting data read instruction signal lines 15a and 15b are ON. Referring to FIG. 4 as an example, when the instruction signal of the setting data read instruction signal 15a is OFF, the process A is not executed, the instruction signal is turned ON, and after the setting data for each port is read, the corresponding processing is performed. Processing A
Becomes executable.

[0028]

The present invention exhibits the following excellent effects.

(1) The number of pins of the CPU control unit LSI and the communication control unit LSI can be reduced. As a result, it is not necessary to use a multi-pin LSI or to further divide the LSI, thereby reducing the cost of the LSI. Further, the size of the substrate on which the LSI is mounted can be reduced.

(2) If the board on which the LSI for the CPU control section is mounted is separated from the board on which the LSI for the communication control section is mounted, the number of signal lines for connection between the boards is reduced. Volume is reduced and costs are lower.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a setting data notification circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an internal circuit of a communication control unit in FIG. 1;

FIG. 3 is a memory area diagram showing a storage area of each setting data in a memory.

FIG. 4 is a timing chart when setting data is read according to the present invention.

FIG. 5 is a memory area diagram showing a storage area of each setting data in a memory according to another embodiment of the present invention.

FIG. 6 is a timing chart when setting data is read in another embodiment of the present invention.

FIG. 7 is a configuration diagram of an internal circuit of a communication control unit according to another embodiment of the present invention.

FIG. 8 is a configuration diagram of an apparatus having a plurality of communication ports.

FIG. 9 is a configuration diagram of a register that stores processing settings for each port.

FIG. 10 is a configuration diagram of a conventional setting data notification circuit.

[Explanation of symbols]

 11 CPU 12 CPU control unit 13 Communication control unit (control unit) 14 Notification memory (memory) 15a, 15b Setting data read instruction signal line

Claims (3)

[Claims] 1. A control unit for performing a predetermined operation for each bit in accordance with setting data composed of a plurality of bits,
In a circuit for notifying a plurality of setting data from the PU, a memory having a predetermined bit width having a plurality of data storage areas between which the CPU writes the setting data and the control unit can read is provided between the CPU and the control unit. Provided, the above CP
U outputs an instruction signal for each setting data to the control unit,
A setting data notification circuit, wherein the control unit reads the contents of the memory for each setting data based on the instruction signal. 2. The bit width of the memory is M / N for the number M of bits of one set data, the CPU writes one set data in N pieces, and the control section divides the set data into N times. 2. The setting data notification circuit according to claim 1, wherein one setting data is read. 3. The instruction signal is a binary level signal, instructing the setting data when changing from one level to the other level, and indicating whether or not the setting data can be executed according to the level. 3. The setting data notification circuit according to claim 1, wherein the control section reads the setting data when the level of the instruction signal changes and performs the operation only when the level of the setting signal is executable.