JPH05334234A - High speed dma transferring device - Google Patents

Abstract

PURPOSE:To attain speed up of a DMA transfer by simultaneously operating a memory read and a memory write in one time of cycle, at the time of the inter-memory transfer of a DMA. CONSTITUTION:At the time of a DMA trasfer, a DMA controller 2 and a decoder 3 simultaneously select arbitrary memory 7 at the origin of transfer and memory 8 at the destination of transfer which carry out the DMA transfer. The DMA controller 2 outputs a memory write (MWR) signal 20 and a memory write (MRO) signal 21 in one cycle, and the decoder 3 outputs a first gate signal 24 and a second gate signal 25 by a DMA trasfer direction control signal 19. Thus, the DMA transfer data are transferred from the memory 7 at the original of transfer through a data bus 11 to the memory 8 of the destination of transfer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a DMA (Direct).
The present invention relates to a memory access transfer, and more particularly to a high-speed DMA transfer device capable of performing high-speed DMA transfer between memories.

[0002]

2. Description of the Related Art Conventionally, this type of memory-to-memory DM is used.
In the A transfer, the DMA controller outputs an address and a control signal to the transfer source memory to output the transfer data from the transfer source memory and latch the transfer data.

Next, the DMA controller outputs the address and the control signal to the transfer destination memory to write the transfer data to the transfer destination memory, which requires two cycles.

[0004]

DISCLOSURE OF THE INVENTION Conventional DMA described above
The transfer requires two cycles of reading the transfer data from the transfer source memory and writing the transfer data to the transfer destination memory, so that the transfer efficiency becomes worse if a faster DMA transfer is desired. There is a problem.

[0005]

High-speed DMA according to the present invention
The transfer device selects a transfer source memory and a transfer destination memory at the same time during DMA transfer, and a means for outputting a memory read signal to the transfer source memory and a memory write signal to the transfer destination memory within one cycle. And means for transferring the DMA transfer data from the transfer source memory to the transfer destination memory via the data bus.

[0006]

According to the present invention, since the DMA transfer between the memories can be performed in one cycle, the DMA transfer can be performed at high speed.

[0007]

1 is a block diagram showing an embodiment of a high speed DMA transfer device according to the present invention. In the figure, reference numeral 1 is a CPU for executing an input / output command, which receives an HLDRO signal 13, an HLDAK signal 14, an I / O write signal 15, I
/ O read signal 16, CPU memory read signal 17, C
The PU memory write signal 18 is output.

A DMA controller (DMAC) 2 includes an HLDAK signal 14, an I / O write signal 15, and an I / O write signal.
O lead signal 16 is input respectively, and HLDRO signal 1
3, the DMA transfer direction control signal 19, the memory write (MWR) signal 20 shown in FIG. 2E, and the memory read (MRD) signal 21 shown in FIG.

Reference numeral 3 is a decoder (DEC), which is an HLDA.
The K signal 14 and the DMA transfer direction control signal 19 are input, and the first chip enable signal 22, the second chip enable signal 23, the first gate signal 24, and the second gate signal 25 are output, respectively.

The decoder (DEC) 3 selects either the first memory or the second memory described below when decoding the upper address from the CPU 1, but the mode is switched by the HLDAK signal 14 at the time of DMA transfer. Thus, the two memories of the first memory and the second memory for performing the DMA transfer are simultaneously selected.

Reference numeral 4 denotes a first gate having gate circuits 4A and 4B, to which a memory write (MWR) signal 20, a memory read (MRD) signal 21 and a first gate signal 24 are input. Reference numeral 5 is a second gate having gate circuits 5A and 5B, to which a memory write (MWR) signal 20, a memory read (MRD) signal 21 and a second gate signal are input.

Reference numerals 6A to 6E are logic OR gates, which are CPU memory read signals 17 and CPU memory write signals required when the CPU 1 executes memory read / memory write to the following first memory and second memory. Enable 18

7 is the first memory, 8 is the second memory, and 9 is C.
A high-order address bus connected between PU1, DMA controller (DMAC) 2 and decoder (DEC) 3, 10 is a low-order address connected between CPU 1, DMA controller (DMAC) 2, first memory 7 and second memory 8. Bus, 11 is CPU1, DMA controller (DMAC)
2, a data bus connected between the first memory 7 and the second memory 8.

FIG. 2 is a schematic diagram of the timing of one cycle of the signal of each part of the high speed DMA transfer. This one cycle consists of four states 26 (S1, S2, S3, S
4), and each state corresponds to one clock of the clock signal shown in FIG. 2B is an address, FIG. 2C is data, FIG. 2D is a memory read (MRD) signal, and FIG. 2E is a memory write (MW).
R) signal, which indicates to execute during one cycle.

Next, the operation of the high speed DMA having the above configuration will be described. First, when a DMA request is generated, the DMA controller (DMAC) 2 sends an H
The LDRO signal 13 is output. Then, the CPU 1 receives the HLDRO signal 13 and outputs the HLDAK signal 14 indicating the state where the bus is released to the DMA controller (DMA).
C) Output to 2.

Upon receiving the HLDAK signal 14, the DMA controller (DMAC) 2 determines that the CPU 1 has released the bus, and starts the DMA operation. Here, a case of performing DMA transfer from the first memory 7 to the second memory 8 will be described.

When in the DMA transfer state, the DMA controller (DMAC) 2 is in advance in advance of the CPU 1 before the DMA transfer.
From the I / O write signal 15, the I / O read signal 16, the address bus and the data bus, the upper address sent to the upper address bus 9 is output to the decoder (DEC) 3.

Therefore, the decoder (DEC) 3 decodes the upper address and outputs the first chip enable signal 22,
The second chip enable signal 23 is output to simultaneously select the first memory 7 and the second memory 8. Thus, DM
At the time of A transfer, the first memory 7 and the second memory 8 are simultaneously selected.

The decoder (DEC) 3 receives the DMA transfer direction control signal 19 output from the DMA controller (DMAC) 2 to input the first gate signal 24.
To the first gate 4 and the second gate signal 25 to the second gate 5.

Therefore, the first gate circuit 4A of the first gate 4 is closed and the second gate circuit 4B is opened. On the other hand, the first gate circuit 5A of the second gate 5 opens and the second gate circuit 5A
B closes. Therefore, DMA controller (DMAC)
2 is a memory read (MRD) signal 21 (FIG. 2).
(See (D)) is input to the first memory 7 via the gate circuit 4B in the open state of the first gate 4 → the logical OR gate 6B to execute the memory read (MRD).

The DMA controller (DMAC) 2
Memory write (MWR) signal 20 output from
(See (E)) is the gate circuit 5 with the second gate 5 opened.
A → input to the second memory 8 via the logical OR gate 6C to execute a memory write (MWR).

The DMA controller (DMAC) 2
Sends the lower address to the first memory 7 and the second memory 8 via the lower address bus 10 from the CPU 1 in a preset transfer direction. In this way, at the same time, the first memory 7 and the second memory 8 are selected, the same lower address is transmitted, the memory read (MRD) signal 21 is transmitted to the first memory 7, and the second memory write (MWR) signal 20 is transmitted.
By executing the sending to the memory 8 within one cycle, the DMA transfer data can be DMA-transferred at high speed from the first memory 7 to the second memory 8 through the data bus 11.

[0023]

As described in detail above, according to the high speed DMA transfer apparatus of the present invention, means for simultaneously selecting the transfer source memory and the transfer destination memory at the time of DMA transfer, and 1
By providing means for outputting a memory read signal to the transfer source memory and outputting a memory write signal to the transfer destination memory within the cycle, DMA transfer between the memories can be reduced to 1
Since it can be performed in cycles, there is an effect that the DMA transfer can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a high speed DMA transfer device according to the present invention.

2 is a schematic diagram of the timing of one cycle of a signal of each unit of the high speed DMA transfer device of FIG.

[Explanation of symbols]

 1 CPU 2 DMA controller (DMAC) 3 Decoder (DEC) 4 First gate 5 Second gate 6A to 6E Logical OR gate 7 First memory 8 Second memory 9 Upper address bus 10 Lower address bus 11 Data bus 11 Data bus

Claims (1)

[Claims] 1. A CPU that outputs an input / output instruction to a DMA controller, a DMA controller that outputs a transfer direction control signal during DMA transfer and outputs a memory write signal and a memory read signal within one cycle, and a plurality of DMA controllers that perform DMA transfer. Memory and arbitrary 2 that transfers at the time of DMA transfer
A decode circuit that outputs an enable signal for simultaneously enabling two memories, receives a transfer direction control signal, and outputs a first gate signal and a second gate signal, and transfers the memory read signal by receiving the first gate signal A first gate opened to output to the original memory, and a second memory opened to receive the second gate signal and output the memory write signal to the transfer destination memory. High-speed DMA transfer device.