JPH10198524A - Hard disk controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a hard disk controller in which plural hard disk devices can be simultaneously operated, and the data of an original hard disk device can be copied to plural copy destination hard disk devices in a short time and verified in a short time. SOLUTION: This device is composed of a main board part 29 which controls the whole device, an extended board part 30 having a main board direction data buffer and a hard disk direction data buffer provided so as to be made correspond to each of plural hard disk devices and a buffer control part, and plural hard disk devices 31-36 connected with the extended board part. Thus, data supplied from the main board part are supplied to the plural had disk devices connected with the extended board part, and they can be simultaneously operated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a hard disk control device, and more particularly to a device for controlling a plurality of hard disk devices. In recent years, the shipment results of personal computers have been increasing. One of the factors is that the installation work of basic software and main application software, which ordinary users were not good at, is now performed in the factory of the manufacturer, so the general user does not need special expertise More and more opportunities to benefit from sophisticated software.

[0002] Another is higher performance and lower cost.
Significant improvement in cost performance due to the simultaneous progress of high performance and low price of hardware including processors. Therefore, it is preferable for a manufacturer to provide a product in consideration of the above two points.
From the viewpoint of software compatibility, hardware often adopts the same or similar architecture among major manufacturers, and it has become difficult to secure an advantage based on hardware prices alone. I have. Therefore,
Reducing costs by improving the efficiency of the manufacturing process greatly affects the superiority of product prices.

[0003] Introducing basic software and application software in a personal computer factory is one of the areas where efficiency is required, and the introduction of highly efficient equipment has an advantage. On the other hand, in order to secure corporate profits, it is necessary to curb capital investment. Therefore, provision of high cost performance equipment is demanded.

[0004]

2. Description of the Related Art FIG. 9 is a block diagram showing an example of a conventional control device for a hard disk drive. In the figure, a main board 1 and a hard disk drive (H
DD) Original HD used by connecting one to one to control boards 2, 3, 4, 5, 6, 7 and HDD control board
D8 and copy destination HDDs 9, 10, 11, 12, and 13. Note that the number of HDD control boards and HDDs is for convenience, and may increase or decrease in actual prior art devices.

When power is applied to the device, the main board 1, the HDD control boards 2, 3, 4, 5, 6, 7 and
The HDDs 8, 9, 10, 11, 12, and 13 start operating. The CPU 14 of the main board 1
The firmware of the ROM 16 is fetched via the PU bus 26, the DISK interface circuit 18 is controlled, and the internal HDD 19 or the floppy disk device 20 is fetched.
From RAM to software to make the entire device function
15 to fetch the software in the RAM 15 and start executing the software. The CPU 14 operates the main board CPU bus 2 by the function of this software.
6, CPU bus to high-speed bus interface circuit 17,
Via the high-speed bus 27, the HDD control boards 2, 3, 4,
Transfer of data that specifies the operations of 5, 6, 7 and the copy destination HD
D9, 10, 11, 12, 13 for data transfer, original HDD and copy destination HDD 9, 10, 11, 1
Receiving data from 2, 13 and RAM of received data
15 is stored.

HDD control boards 2, 3, 4, 5, 6, 7
CPU 22 fetches the firmware in the ROM 24 and executes the instruction. The CPU 22 receives data defining the operation of the HDD control board via the HDD control board CPU bus 28, the high-speed bus-to-CPU bus interface circuit 21, and the high-speed bus by the function of the firmware, and stores the data in the RAM 23. Thereafter, the data stored in the RAM is appropriately analyzed, and in accordance with the result, the HDD interface circuit 25 is controlled via the HDD control board CPU bus 28 to write the data to the RAM 23 or read the RAM 23 from the HDD. Data of the HDD control board CPU bus 28 and the high-speed bus toCP
The data is transferred to the main board 1 via the U bus interface circuit 21 and the high-speed bus 27. After that, the HDD control boards 2, 3, 4, 5, 6, and 7 transfer the respective HDD operation status data to the main board 1.

As described above, in the device according to the prior art,
Main board 1 and HDD control boards 2, 3, 4, 5,
By transferring data between each other and managing the entire operation by the software of the main board 1, the HD
It is considered to function as a D data copying device.

[0008]

However, the conventional device has three problems. First, this device is to be a multi-CPU system, and has a high-speed bus and C
The need to provide a PU bus interface on each board tends to increase the cost.

Second, data transfer between the main board 1 and the HDD control boards 2, 3, 4, 5, 6, 7 is performed by a high-speed bus 2
7, the data that can be transferred to and from the main board 1 in certain situations are the HDD control boards 2, 3, 4, 5,
There is only one board out of 6,7. Therefore,
In order to operate efficiently as a whole device, it is necessary to set the HDD so that each HDD appears to be operating at the same time.
It is necessary to transfer data using a bus that is sufficiently fast with respect to the operation speed of the DD. However, even with a bus having sufficient performance with the current number of HDD control boards, by increasing the number of HDD control boards and HDDs, the transfer speed of the bus becomes a bottleneck, and the data holding time of the HDD control board becomes longer. And the performance cannot be improved in proportion to the scale expansion. For this reason, there is a problem that the potential for increasing the scale of the device is small.

Third, in the step of verifying whether the data written in the copy destination HDDs 9 to 13 matches the contents of the original HDD, first, the data of the original HDD 8 is stored in a certain area of the RAM 15 and Copy destination HDD 9
To 13 are stored in independent areas of the RAM 15, and the CPU 14 executes software for verifying whether the data of the original HDD matches the data of each copy destination HDD. Here, there is a problem that, in addition to the sequential transfer of data from the number of HDDs of the copy destination + 1 HDD, the operation time of the software and the additional time are required.

[0011] The present invention has been made in view of the above points,
It is an object of the present invention to provide a hard disk control device capable of simultaneously operating a plurality of hard disk devices, copying data of an original hard disk device to a plurality of copy destination hard disk devices in a short time, and verifying the data in a short time.

[0012]

According to a first aspect of the present invention, there is provided a control interface for inputting / outputting control data,
A main board unit having a hard disk interface for inputting and outputting hard disk data and controlling the entire device; and a main board unit provided for each of the plurality of hard disk devices and supplying data supplied from the hard disk device to the hard disk interface. One of a board direction data buffer, a hard disk direction data buffer for supplying data supplied from the hard disk interface to the hard disk device, and a plurality of main board direction data buffers in accordance with control data supplied from the control interface An extension board unit having a buffer control unit for selecting and operating one of the plurality of hard disk direction data buffers and operating one of the plurality of hard disk direction data buffers; The hard disk drive to become more.

Therefore, it is possible to supply data supplied from the main board to a plurality of hard disk drives connected to the extension board and operate them simultaneously. According to a second aspect of the present invention, in the hard disk control device according to the first aspect, the main board unit simultaneously operates a plurality of hard disk devices connected to the expansion board unit.

For this reason, it becomes possible to read or write simultaneously with a plurality of hard disk devices.
According to a third aspect of the present invention, in the hard disk drive according to the second aspect, the main board unit reads data read from an original hard disk device connected to the extension board unit to a plurality of copies connected to the extension board. Copy to the hard disk drive at the same time.

[0015] Therefore, data can be copied to a plurality of hard disk devices in a short time. According to a fourth aspect of the present invention, in the hard disk control device according to the third aspect, the expansion board unit receives the data read from the original hard disk device and the data read from the plurality of copy destination hard disk devices at the same time. There is a data comparing means for comparing each read data with each other to determine an error when the read data is different.

Therefore, it is possible to verify in a short time whether or not the data of the plurality of copy destination hard disk devices is the same as the data of the original hard disk device. According to a fifth aspect of the present invention, in the hard disk control device according to any one of the first to fourth aspects, the expansion board unit performs a logical operation on each of status data and control signals supplied from a plurality of connected hard disk devices. And a timing adjuster for generating a single status data and control signal to be supplied to the main board unit.

Therefore, even when a plurality of hard disk drives are operated at the same time, it is equivalent to operating a single hard disk drive in the main board section, and simultaneous control of a plurality of hard disk drives becomes possible. According to a sixth aspect of the present invention, in the hard disk control device according to the fifth aspect, the timing adjustment means controls status data and control corresponding to a hard disk device connected to an unselected hard disk direction data buffer by the buffer control unit. Generate a default value for each signal.

Thus, erroneous status data and control signals are not supplied to the main board unit by an unselected hard disk device, and simultaneous control of a plurality of selected hard disk devices becomes possible. According to a seventh aspect of the present invention, in the hard disk control device according to the fifth or sixth aspect, the timing adjustment means sets default values of status data and control signals corresponding to a hard disk device not connected to the extension board unit. Occur.

Thus, even if there is a hard disk drive that is not connected to the expansion board unit, erroneous status data and control signals are not supplied to the main board unit, and simultaneous control of a plurality of connected hard disk units is achieved. It becomes possible. According to an eighth aspect of the present invention, in the hard disk control device according to the first aspect, the control interface of the main board unit has a serial interface for performing low-speed data communication and a parallel interface for performing high-speed data communication.

[0020] Therefore, the software is simplified because low-speed communication is performed by using a serial interface to transmit commands and the like that have extra time, and data reading from the original hard disk device and data transfer to the copy destination hard disk device are performed. Switching between writing and writing can be performed at high speed because communication is performed using the parallel interface.

According to a ninth aspect of the present invention, in the hard disk control device according to the first aspect, a hard disk device is mounted instead of the plurality of hard disk devices connected to the expansion board, and A plurality of pseudo hard disk devices, which are computers that are virtually recognized as hard disk devices, are connected.

For this reason, a plurality of computers having a built-in hard disk drive are connected to the extension board section as a pseudo hard disk drive, and data from the original hard disk drive is copied to the hard disk drive built in the plurality of computers and verified. And the workability of copying and verification can be improved.

According to a tenth aspect of the present invention, in the hard disk control device according to the first aspect, the main board unit is connected to a computer, and the computer accesses a plurality of hard disk devices connected to the expansion board unit. .

Therefore, the plurality of hard disk devices can be recognized as one hard disk device by the computer, and the capacity of the hard disk device connected to the computer can be increased. Claim 11
In the hard disk control device according to claim 10, the same data is written to the plurality of hard disk devices, and when an error occurs in data read from any hard disk device, data is read from another hard disk device. Is performed.

For this reason, the hard disk drive is duplicated,
Or more multiplexing can be realized simply and at low cost.

[0026]

FIG. 1 is a block diagram showing a first embodiment of the apparatus according to the present invention. In the figure, the apparatus of the present invention includes a main board 29 as a main board, an HDD extension board 30 as an extension board, an original HDD 31, a copy destination H
DD32,33,34,35,36. However, the number of copy destination HDDs is a number for convenience, and in reality, H is set so that more copy destination HDDs can be connected.
The inside of the DD extension board is configured.

In the figure, when the power is turned on to the apparatus, the CPU 37 of the main board 29 starts fetching the firmware stored in the ROM 39, executes the firmware, and executes the hard disk interface via the main board CPU bus 43. And reads software for causing the entire device to function as an HDD copying device from the floppy disk device 42, and starts executing the software. First, the CPU 37 controls the serial / parallel interface circuit 40 as a control interface via the main board CPU 43, and sets the hardware from the serial interface 44 to the HDD extension board 30 in a state suitable for the operation to be performed. To send information. During this time, the C of the HDD extension board 30
The PU 49 fetches and executes the firmware in the ROM 47, and executes the serial interface circuit (serial I / O).
F) The information input from 51 is monitored.

When recognizing the information input from the serial IF 51, the CPU 49 analyzes the content of the information and sets any one of the HDD select register 53, the operation mode register 54, and the bus select register 55 according to the result. Then, the hardware of the HDD extension board 30 is set so as to be able to cope with subsequent operations. The HDD select register 53 sets information supplied from the serial interface 44 for determining an HDD to be controlled. The operation mode register stores the data from the original HDD to the copy destination HD.
Input information as to whether to copy data to D (hereinafter referred to as copy mode), to compare the contents of the original HDD with each copy destination HDD (hereinafter referred to as the comparison mode), and to enable the original HDD write protection circuit. It is set when you do.

The bus select register 55 controls the main board direction data buffers 66a to 66f of the HDDs 31 to 36 in order to prevent collision of bus signals when information for determining an HDD to be controlled is input. Is set. The buffer EN signal generation circuit 58 includes an HDD select register 53, an operation mode register 54, a bus select register 55, an original / copy destination selection circuit 56, and a status register access detection circuit 60.
From the data buffers 64a to 64f,
Generate enable signals 66a-66f and supply them.

The buffer EN signal generating circuit 58 has a status register or an alternate status register (these registers are provided in the HDDs 31 to 36, respectively).
Main board 2 (read from main board as appropriate)
9 is read, a signal is supplied from the status register access detection circuit 60 which outputs a true signal, and when the signal from the status register access detection circuit 60 is false, another input signal causes The enable signal is supplied to only necessary ones of the data buffers 66a to 66f and the HDD direction data buffers 64a to 64f.

The buffer supplied with the enable signal can output the input signal, and the output of the buffer not supplied becomes a high impedance state in which the value is neither 1 nor 0 regardless of the input signal. , The circuit preceding the buffer is in the same state as virtually nonexistent. This allows the main board 29 to transmit the command and select the HDD to which data is to be transmitted and received.
The registers 52 to 55 and the buffer EN signal generation circuit 58 correspond to a buffer control unit.

In order to execute the simultaneous control of a plurality of HDDs successfully, it is necessary to create a timing capable of controlling all the target HDDs and to realize a state transmission when only a specific HDD is in a unique state. There is. This is realized by the status data timing adjust circuit 6
1 and a timing adjustment means comprising a control signal timing adjustment circuit 62.

The status data timing adjust circuit 61 enables the status buffer 65 by the status register access detection circuit 60 when the status register or the alternate data register is read from the CPU 37, and enables output to the main board 29. Become. The status data is 8-bit data having meaning for each bit, and indicates control, data transfer timing, and a state related to an error that has occurred during operation. The status data timing adjust circuit 61 receives signals from all the HDDs 31 to 36 including the original HDD 31, and outputs true when the control and data transfer timings become true for all the HDDs. Further, the circuit is configured such that, when a signal from the HDD is not input due to a small number of connected HDDs, the input is true. As for a bit indicating a state related to an error that has occurred during operation, true is output if at least one of them is true. When a signal from the HDD is not input due to a small number of connected HDDs, the circuit is configured so that the input becomes false.

The signal types output from the control signal timing adjustment circuit 62 include an interrupt signal (hereinafter referred to as an interrupt signal) indicating an operation end timing, a signal indicating that 16-bit data transfer is being executed (hereinafter referred to as data transfer), and a CPU.
There is a signal (hereinafter referred to as a WAIT signal) for requesting a wait for 37. During interrupt signal and data transfer,
It is set to be true when the inputs from all HDDs 31 to 36 are true. When a signal from the HDD is not input due to a small number of connected HDDs, the circuit is configured so that the input is true.

As for the WAIT signal, basically, if at least one HDD has a signal that makes the signal true, the signal is output true. The WAIT signal is a signal to be output from the HDD when the HDD cannot appropriately respond to the CPU 37. If the WAIT signal does not become true within a certain time from the signal indicating the CPU 37 accessing the HDD, the WAIT signal is output.
37 does not accept the WAIT signal. In this situation, the data transfer timing between the CPU 37 and the HDD is shifted, and the CPU 37 receives incorrect data,
It becomes a state where wrong data is written to the HDD.
Moreover, in the HDD extension board 30 of the present embodiment, the WAI is reduced due to the signal stabilization and the signal delay of the buffers 66a to 66f used for the purpose of realizing the HDD select function.
Not only is the T signal not accepted, but also when the HDD does not output the WAIT signal, it is not possible to secure an appropriate data transfer timing. Therefore, as shown in FIGS.
7 is generated in the HDD expansion board.

FIG. 2 is a timing chart showing a method of creating a WAIT signal to be transmitted to the CPU 37 when the HDD outputs the WAIT signal. With respect to the maximum time a from the fall of the HDD access signal of the CPU shown in FIG. 2A to the fall of the WAIT standard timing shown in FIG. The WAIT of the output of the actual HDD shown in FIG.
If the time b is exceeded when it reaches the 7th, HD
In the D extension board 30, the WAIT signal shown in FIG. 3D is generated and held for a time c having a margin with respect to the time b, and the signals shown in FIGS. A WAIT signal to be transmitted to the CPU shown in FIG.

FIG. 3 is a timing chart showing a method of creating a WAIT signal to be transmitted to the CPU 37 when the HDD does not output the WAIT signal. Here, the maximum time a from the rise of the HDD access signal of the CPU shown in FIG. 3 (A) to the fall of the WAIT standard timing shown in FIG. 3 (B) corresponds to the time a + c shown in FIG. 3 (C). A signal of 0 is generated and output to the CPU 37.

FIG. 4 is a block diagram showing one embodiment of the status data timing adjustment circuit 61. The status data timing adjustment circuit 61 performs two types of processing depending on the content of the signal to be processed. The first type is a process for a signal that needs to be asserted to the main board 29 if at least one of the operating HDDs has asserted a signal, and the HDD is unselected or unconnected. Disk interface port (H
This configuration prevents the condition for asserting a signal to the main board 29 from being improperly set by the connection terminals of the DD extension board 30 for the HDDs 31 to 36).

The signal subjected to this first type of processing is H
These are a busy signal indicating that the DD cannot accept a command and an error notification signal indicating that an error has occurred in the HDD. The above signals output from the HDDs 31 to 36 are supplied to the buffer circuits 100 to 105, respectively. The buffer circuits 100 to 105 have the same configuration, the input terminal is grounded via a resistor, the output terminal is connected to a positive power supply (+5 V) via a resistor, and the control terminal is connected to the HDD EN from the buffer EN signal generation circuit 58. It is composed of an inverter supplied with a corresponding enable signal.

Each of the buffer circuits 100 to 105 has a corresponding H
If the DD enable signal is asserted (HDD selection), the supplied signal is inverted and the next inverter 1
07 to 112, and if the enable signal is deasserted (HDD not selected), the value 1 is fixedly supplied to the next-stage inverters 107 to 112 because the output terminal is connected to the power supply. When the HDDs 31 to 36 are not connected, the value 0 is supplied because the input terminals of the buffer circuits 100 to 105 are grounded.

For this reason, the inverters 107 to 112 corresponding to the unselected or unconnected HDD always output the value 0,
The outputs of the inverters 107 to 112 are supplied to an OR circuit 114. The OR circuit 114 outputs the value 0 only when all the supplied signals have the value 0, and outputs the value 1 in other cases. Therefore, when at least one of the selected HDDs asserts the busy / error notification signal, the busy / error signal is asserted to the main board 29. Also, since the busy signal has a value of 0 when the HDD is not connected, the HDD uses a busy signal of 1 for a while at the time of starting up the HDD, making a check immediately after turning on the HDD power, and instantaneously. The presence or absence of the HDD connection can be determined.

The second type is a process for a signal to be asserted to the main board 29 only when all active HDDs have asserted a signal.
Does not prevent the condition of asserting the signal to the main board from being set by the unselected or unconnected disk interface port. The signal subjected to the second type of processing is a control timing signal,
The control timing signals output from each of the six
It is supplied to each of 15 to 120. Buffer circuits 115-
Reference numeral 120 denotes the same configuration, which is configured by a buffer whose output terminal is connected to a positive power supply (+5 V) via a resistor and whose control terminal is supplied with an enable signal corresponding to the HDD from the buffer EN signal generation circuit 58. .

The buffer circuits 115 to 120 have corresponding H
If the DD enable signal is asserted (HDD is selected), the supplied signal is output. If the enable signal is deasserted (HDD is not selected), the output terminals are connected to the power supply, so that the buffer circuits 115 to 120 are connected. Outputs a fixed value of 1. Further, the buffer circuits 115 to 120 corresponding to the unconnected HDDs always output the value 1, and the outputs of the buffer circuits 115 to 120 are supplied to the AND circuit 123. The AND circuit 123 outputs the value 1 only when all the supplied signals have the value 1, and outputs the value 0 in other cases. Therefore, all the connected and selected H
When the DD asserts the control timing signal, the control timing signal is asserted to the main board 29.

FIG. 5 is a block diagram showing one embodiment of the control signal timing adjust circuit 62. The control signal timing adjust circuit processes the WAIT signal and the interrupt request signal during data transfer, and supplies the value 1 to the main board when the inputs from all the HDDs 31 to 36 are the value 1. However, in the drawing, since the signal is a negative logic signal during the data transfer and the WAIT signal to which the bar is added, it is considered as a negative logic input OR logic. That is, when one or more HDDs assert a signal of value 0 (assert), the operation is performed so as to assert the signal to the main board 29. The WAIT signal is output after being synthesized with the generated signal of this circuit.

The WAIT signal output from the HDDs 31 to 36 and the interrupt request signal during data transfer are supplied to the buffer circuits 132 to 137, respectively. Buffer circuit 132
137 have the same configuration, the output terminal is connected to a positive power supply (+5 V) via a resistor, and the buffer E is connected to the control terminal.
It is composed of a buffer supplied with an enable signal for the HDD from the N signal generation circuit 58. When the enable signal of the corresponding HDD is asserted (HDD selection), the buffer circuits 132 to 137 output the supplied signal, and the enable signal is deasserted (HDD not selected).
Then, since the output terminal is connected to the power supply, the buffers 132 to 137 fixedly output the value 1. Further, the buffer circuits 132 to 137 corresponding to the unconnected HDD always output the value 1, and the outputs of the buffer circuits 132 to 137 are supplied to the AND circuit 139. The AND circuit 139 outputs the value 1 only when all the supplied signals have the value 1,
Otherwise, it outputs the value 0.

The flip-flop 141 is supplied with a negative logic HDD access signal from the DISK interface circuit 41 to the clock input terminal, is supplied with the value 1 to the data input terminal, and clear-inputs a signal obtained by delaying the HDD access signal by the delay circuit 142. It is supplied to the terminal. Thus, when the flip-flop 141 is supplied with the HDD access signal, it generates a negative logic WAIT signal,
The IT signal is supplied to the AND circuit 140 and the AND circuit 1
The logical OR of the WAIT signal supplied from 39 and negative logic is obtained and supplied to the control signal output buffer 63 of FIG.

Next, the operation of the apparatus shown in FIG. 1 will be described. This apparatus performs a recognition step of a connected HDD (hereinafter, a recognition step), a copying step of copying the contents of an original HDD to a copy destination HDD (hereinafter, a copying step), and a step of copying the copied contents to the contents of the original HDD. It consists of a verification step (hereinafter referred to as a verification step).

In the recognition step, first, the CPU 37 causes the serial interface 44 to cause the original / copy destination selection circuit 56 to output data for controlling the original HDD 31 and outputting a signal for data transmission / reception. Data is transmitted to the register 54 so as to set the copy mode and the original HDD write protection circuit 59 as valid,
The DD select register 53 transmits data so that only the original HDD 31 is selected, so that when the output of the status register access circuit 40 is false, the HDD direction buffer 64a of the original HDD 31 and the main board direction data buffer are output. Only 66a becomes effective, and control of the original HDD 31 and transmission and reception of data become possible. In this state, a command for acquiring HDD parameters such as the model number, capacity, block length, and number of blocks of the HDD is given. If this command ends normally, it is determined that the original HDD 31 is present and that normal operation is possible, and the operation shifts to the work of recognizing the copy destination HDD.

Next, the CPCU 37 sends data from the serial interface 44 so that the original / copy destination selection circuit 56 outputs a signal for controlling one of the copy destination HDDs and transmitting and receiving data. Data is transmitted to the HDD select register 53 so that only an arbitrary copy destination HDD to be controlled and transmitted / received is set. One copy destination H is stored in the HDD select register 53.
At the same time as setting of the DD, the firmware function of the HDD extension board 30 uses the HDD select register 53.
The bus select register 55 is set so that the data buffer in the main board direction of the copy destination HDD and the data buffer in the HDD direction specified by (1) become valid.

The bus select register 55 is originally
When only a plurality of HDDs are selected, to prevent a plurality of mainboard direction data buffers from becoming effective and causing a bus collision, one of the selected H
Used to enable only the mainboard direction data buffer for DD. In this state, when the output of the status register access detection circuit 60 is false, the designated H
Only the DD direction data buffer and the main board direction data buffer are enabled, and control of the original HDD 31 and transmission / reception of data become possible. Here, a command for acquiring HDD parameters is issued, the command ends normally, and the original H is deleted except for a unique value such as a serial number.
If the parameters match the DD parameters, the copy destination HDD
Is valid. Hereinafter, similarly, the recognition process is completed for other copy destination HDDs by performing the recognition work.

It should be noted in the recognition process that the maximum number of copy destination HDDs is not always connected to the HDD expansion board 30, and it is a method that simply expects a response from the HDDs. This is because when the HDD is not connected, it cannot be recognized that the HDD is not connected until after a relatively long time-out time has elapsed. This is because the HDD may not accept a command for 30 seconds when the power is turned on. Therefore, in the apparatus of the present invention, a method of removing unconnected portions from control targets in advance by the following method before acquiring HDD parameters is adopted.

The HDDs 31 to 36 set the busy bit of the status register to true for about 30 seconds or less in the power-on sequence. Therefore, by configuring the circuit of the HDD expansion board 30 such that when the status register is read in a state where the HDD is not connected, the busy is false and the signal indicating that the command can be issued becomes true, so that the busy is increased. Is true, it can be determined that the HDD is connected. If the busy is false, an attempt is made to issue a command to the drive, and if a normal response is obtained, it is determined that the HDD is present, and if not, it is determined that the HDD is not connected. Busy is fake,
If the HDD is energized and connected, a response to the command occurs immediately, and it is possible to determine that there is no response due to no connection after a short time-out period.

In the copying process, the operation mode register 54 is set so as to enable the copy mode and the original HDD write protection circuit 59 so that the contents of the original HDD 31 can be read even if a circuit malfunction or control error occurs. Try to prevent destruction. In the copy mode, the input from the original / copy selection circuit 56 becomes valid in the buffer EN signal generation circuit 58. The HDD select register 53 contains the original HDD
31 and a copy destination HDD (for example, 32-3
6) is specified, and the signal supplied from the original / copy destination selection circuit 56 to the buffer EN signal generation circuit 58 is the original HD
By selecting D, the buffer EN signal generation circuit 58
Outputs a signal for enabling the HDD direction data buffer 64a of the original HDD.

In the bus select register 55, the original HD
The mainboard direction data buffer 66a of D is set so that only one mainboard direction buffer (for example, 66b) in the copy destination HDD is enabled, and the original // copy destination selection circuit 56 selects the original. Therefore, the buffer EN signal generation circuit 58 outputs a signal for enabling the main board direction buffer 66a of the original HDD. Accordingly, the bidirectional bus of the original HDD is enabled, and data is read from the original HDD under the control of the main board 29.

Next, when the original / copy destination selection circuit 56 is controlled to select the copy destination, the HDD direction data buffers 64b to 64f of all the copy destination HDDs specified by the HDD select register 53 become valid, and the bus The main board direction data buffer 66b of one copy destination HDD specified by the select register 55 becomes valid. In this state, the read data is ready to be written to the designated copy destination HDD. However, in order to perform simultaneous control of a plurality of HDDs successfully, it is necessary to create a timing that can control all target HDs. It is necessary to realize a state transmission when only a specific HDD is in a unique state. This is realized by the status data timing adjust circuit 61 and the control signal timing adjust circuit 62.

The status data is transferred to the main board 29 by the status register access detection circuit 60 when the status register is read from the CPU 37 and the status buffer 65 is enabled. The control signal is generated asynchronously to the CPU 37 depending on the state of the HDD. The status data is 8-bit data having meaning for each bit, and indicates control, data transfer timing, and a state related to an error that has occurred during operation. The control signal uses an independent signal line,
There are an interrupt signal indicating the operation end timing and a WAIT signal to the CPU during data transfer. Of the control, data transfer, and operation end timings, the signal is made true for the main board when the corresponding signal is true for all the target HDDs, and true for at least one of the other HDDs if true. ing. When an error occurs, a retry is performed for each unit, and the HDD in which the error has occurred can be specified.

In this way, it is possible to simultaneously operate a plurality of HDDs with a single control, and by controlling the writing and transferring the writing data, all the copy destination HDDs 32 to
The data is copied to the memory 36 at the same time. In addition, HDD
In order to copy the entire data, it is necessary to repeat the data read from the original HDD 31 and the copy to the copy destination HDDs 32 to 36.
With the setting using the parallel interface 45, the bus switching is performed directly in a circuit, thereby shortening the switching time between data reading and copying.

The verification step can be executed by setting the verification mode in the operation mode register of the HDD extension board. Original HDD 31 and all designated copy destinations H
The DD (for example, 32-36) HDD direction data buffer 64a-64f and the original HDD main board direction data buffer 66a become effective. The status data timing adjustment circuit 61 and the control signal timing adjustment circuit 62 function in the same manner as in the copying process.
Under the read control of 37, the original HDD 31 and all the designated copy destination HDDs execute reading, and the read data is transmitted to the data comparing circuit 5 as data comparing means.
7, it is checked whether the data of each copy destination HDD matches the data of the original HDD. If there is an error, the bit corresponding to the error occurrence copy destination HDD of the error register 52 is set, and the CPU 49 notifies the main board via the serial interface. After an appropriate time, the CPU 37 instructs, via the serial interface 44, that the copy destination HDD whose content does not match the original HDD is excluded from the verification target.

FIG. 6 is a block diagram showing a second embodiment of the apparatus of the present invention. In this embodiment, pseudo HDDs 80, 81, 82, 83 and 84 are connected in place of the HDDs 32 to 36 in order to further improve the workability with respect to the first embodiment. Main board 29, HDD expansion board 30, and original HDD
31 is the same as that of the first embodiment, and the description is omitted.
D80 to D84 will be described. Usually, the pseudo HDD is configured by mounting an extended DISK interface that enables connection of an external HDD to a computer device itself such as a personal computer.

FIG. 7 is a block diagram showing one embodiment of the pseudo HDD. In the figure, a CPU 86 transmits an R signal via a CPU bus 94, a bus control circuit 87, and a local bus 95.
Check the program of OM89, the whole is pseudo HDD
Software to function as a CPU bus 9
4. The data is loaded from the floppy disk drive 93 to the RAM 88 via the bus control circuit 87, the local bus 95, and the disk interface circuit 90. Next, R
The software loaded on the AM 88 is fetched and the software is executed. The software connects the extended DISK interface circuit 91 and the control device (the main board 29 and the HDD) connected to the HDD interface 93.
The extension board 30) functions to recognize that the HDD is connected.

Hereinafter, functions of software for realizing this will be described. The purpose of pseudo HDD is pseudo H
For the control device to which the DD is connected, the HDD 9
HDD 2 while recognizing it as if
Performing the control expected by the control device on 92,
An object of the present invention is to enable access to the HDD 92 while the HDD 92 is mounted. For this purpose, the pseudo HDD software first obtains the HDD parameters of the HDD 92 and, after an appropriate time, the control device executes the same type of control as the pseudo HDD.
Prepare to run against.

Also, before acquiring the HDD parameters, the software controls the extended DISK interface circuit 91 so as to notify the control device that it cannot respond. After acquiring the HDD parameters, control is performed so as to indicate that response to the control from the control device is possible. Thereafter, control corresponding to the control content from the control device is performed on the HDD 92, and the HDD 92 operates while giving the operation state of the HDD 92 to the control device. The original HDD
Needless to say, the pseudo HDD 31 may be replaced.

FIG. 8 is a block diagram showing a third preferred embodiment of the device according to the present invention. In the figure, a main board 29 is provided in a computer main body 143, and a connection card 145 to which an HDD can be connected is mounted. And the computer body 1
43, a disk expansion device 146 is provided outside the main board 29 and the HDD board 3 in the disk expansion device 146.
0 through the parallel interface 44 and the serial interface 45, and the connection card 145 is connected to the H
The DD extension board 30 is connected by the HDD interface 46.

The disk expansion device 146 is controlled by an HDD expansion board 147 and a device driver which is software connected on the basic software of the computer main body 143 composed of the HDDs 148 to 153. Is accessed. From the viewpoint of the basic software of the computer body 143, the HDD is always recognized as one,
Depending on the device driver, multiple HDDs 148-
153 are recognized and made available individually, or
It can be used as one HDD having the sum of the capacities of the DDs 148 to 153.

The HDD extension board 30 according to the present invention
Simultaneous writing function to multiple HDDs and individual HD
With the function of reading data from D, the following usage method can be considered. In a computer system that requires multiplexing of data for security, data is simultaneously written to a plurality of HDDs, and data is read from one of the HDDs. If an error occurs when reading data, it is possible to switch the HDD to be read so as to read data from another HDD, and it is low cost even if triple or more multiplexing is necessary. It is possible to construct a possible data multiplexing system.

[0066]

As described above, the first aspect of the present invention provides
It has a control interface for inputting and outputting control data and a hard disk interface for inputting and outputting hard disk data.The main board section controls the entire device. A main board direction data buffer for supplying data to the hard disk interface, a hard disk direction data buffer for supplying data supplied from the hard disk interface to the hard disk device, and a control data supplied from the control interface. A buffer control unit that selects and operates any one of the plurality of mainboard direction data buffers and selects and operates one or more of the plurality of hard disk direction data buffers. And board portion, the more the plurality of hard disk devices connected to the expansion board unit.

Therefore, it is possible to supply data supplied from the main board unit to a plurality of hard disk devices connected to the extension board unit, and to operate them simultaneously. According to a second aspect of the present invention, in the hard disk control device according to the first aspect, the main board unit simultaneously operates a plurality of hard disk devices connected to the extension board unit.

For this reason, it is possible to simultaneously read or write in a plurality of hard disk devices.
According to a third aspect of the present invention, in the hard disk device according to the second aspect, the main board unit reads data read from an original hard disk device connected to the extension board unit to a plurality of data connected to the extension board. Is simultaneously copied to the destination hard disk drive.

Therefore, data can be copied to a plurality of hard disk drives in a short time. Also,
According to a fourth aspect of the present invention, in the hard disk control device according to the third aspect, the expansion board unit receives the data read from the original hard disk device and the data read from the plurality of copy destination hard disk devices at the same time. There is a data comparing means for comparing each read data with each other to determine an error when the read data is different.

Therefore, it can be verified in a short time whether or not the data of the plurality of copy destination hard disk devices is the same as the data of the original hard disk device. Claim 5
In the hard disk control device according to any one of claims 1 to 4, the expansion board unit performs a logical operation on each of status data and control signals supplied from a plurality of connected hard disk devices. A timing adjuster for generating a single status data and control signal to be supplied to the main board unit;

Therefore, even if a plurality of hard disk drives are operated at the same time, it is equivalent to operating a single hard disk drive in the main board section, and simultaneous control of a plurality of hard disk drives becomes possible. Claim 6
In the hard disk control device according to the fifth aspect, in the hard disk control device according to the fifth aspect, the timing adjustment means includes a status data and a control signal corresponding to a hard disk device connected to an unselected hard disk direction data buffer by the buffer control unit. Generate a default value.

As a result, erroneous status data and control signals are not supplied to the main board unit by an unselected hard disk device, and simultaneous control of a plurality of selected hard disk devices becomes possible. According to a seventh aspect of the present invention, in the hard disk control device according to the fifth or sixth aspect, the timing adjustment means includes a status data and a control signal corresponding to a hard disk device not connected to the expansion board unit. Generate a value.

As a result, even if there is a hard disk drive not connected to the expansion board unit, erroneous status data and control signals are not supplied to the main board unit, and simultaneous control of a plurality of connected hard disk units can be performed. It becomes possible. The invention described in claim 8 is the first invention.
In the hard disk control device described above, the control interface of the main board unit has a serial interface for performing low-speed data communication and a parallel interface for performing high-speed data communication.

For this reason, the software is simplified because low-speed communication is used to communicate a command or the like having a sufficient time in the serial interface using the serial interface. In addition, data can be read from the original hard disk drive and data can be transferred to the copy destination hard disk drive. Switching between writing and writing can be performed at high speed because communication is performed using the parallel interface.

The invention according to claim 9 is the first invention.
The hard disk control device according to claim 1, wherein a hard disk device is mounted in place of the plurality of hard disk devices connected to the extension board, and the pseudo hard disk device is a computer that is pseudo-recognized as a hard disk device with respect to the main board unit. Are connected.

For this reason, a plurality of computers having a built-in hard disk drive are connected to the extension board as pseudo hard disk drives, and data from the original hard disk drive is copied to the hard disk drive built in the plurality of computers and verified. And the workability of copying and verification can be improved.

According to a tenth aspect of the present invention, in the hard disk control device according to the first aspect, the main board unit is connected to a computer, and a plurality of hard disk devices connected from the computer to the expansion board unit. Have access.

Thus, a plurality of hard disk devices can be recognized as one hard disk device by the computer, and the capacity of the hard disk device connected to the computer can be increased. According to an eleventh aspect of the present invention, in the hard disk control device according to the tenth aspect, when the same data is written to the plurality of hard disk devices and an error occurs in data read from any of the hard disk devices, another hard disk control device is used. Read data from the device.

For this reason, the hard disk drive is duplicated,
Or more multiplexing can be realized simply and at low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram of the device of the present invention.

FIG. 2 is a timing chart for explaining generation of a WAIT signal.

FIG. 3 is a timing chart for explaining generation of a WAIT signal.

FIG. 4 is a block diagram of a status data timing adjustment circuit.

FIG. 5 is a block diagram of a control signal timing adjustment circuit.

FIG. 6 is a block diagram of the device of the present invention.

FIG. 7 is a block diagram of a pseudo HDD.

FIG. 8 is a block diagram of the device of the present invention.

FIG. 9 is a block diagram of a conventional device.

[Explanation of symbols]

 29 Main board 30 HDD expansion board 31 Original HDD 32 to 36 Copy destination HDD 37,49 CPU 38,48 RAM 39,47 ROM 40 Serial / parallel interface circuit 41 DISK interface circuit 42 Floppy disk 43,50 CPU bus 44 Serial interface 45 Parallel interface 46 HDD interface 51 Serial IF 52 Error register 53 HDD select register 54 Operation mode register 55 Bus select 56 Original / copy destination selection circuit 57 Data comparison circuit 58 Buffer EN signal generation circuit 60 Status register access detection circuit 61 Status data timing adjustment Circuit 62 Control signal timing adjust circuit 64a to 64f HDD direction data buffer 66a-66f Main board direction data buffer

Claims (11)

[Claims] 1. A main board unit having a control interface for inputting / outputting control data, a hard disk interface for inputting / outputting hard disk data, and controlling the entire apparatus, and being provided corresponding to each of the plurality of hard disk apparatuses. A mainboard direction data buffer for supplying data supplied from the hard disk device to the hard disk interface, a hard disk direction data buffer for supplying data supplied from the hard disk interface to the hard disk device, and a data buffer supplied from the control interface. Buffer control for selecting and operating one of a plurality of main board direction data buffers according to control data and selecting and operating one or more of a plurality of hard disk direction data buffers Hard disk control device comprising an expansion board section, to become more and more hard disk devices connected to the expansion board portion having and. 2. The hard disk control device according to claim 1, wherein the main board unit simultaneously operates a plurality of hard disk devices connected to the extension board unit. 3. The hard disk device according to claim 2, wherein the main board unit reads data read from an original hard disk device connected to the expansion board unit and a plurality of copy destination hard disk devices connected to the expansion board. A hard disk control device characterized by simultaneous copying to a hard disk. 4. The hard disk control device according to claim 3, wherein the extension board unit reads the data read from the original hard disk device and simultaneously reads the data from the plurality of copy destination hard disk devices. A hard disk control device comprising: a data comparison unit that compares data with each other and makes an error when the data is different. 5. The hard disk control device according to claim 1, wherein the expansion board unit performs a logical operation on each of status data and control signals supplied from a plurality of connected hard disk devices to perform the logical operation. A hard disk control device comprising timing adjustment means for generating a single status data and control signal to be supplied to a main board unit. 6. The hard disk control device according to claim 5, wherein the timing adjustment means sets defaults of status data and control signals corresponding to a hard disk device connected to a non-selected hard disk direction data buffer by the buffer control unit. A hard disk control device for generating a value. 7. The hard disk control device according to claim 5, wherein the timing adjustment means generates default values of status data and control signals corresponding to a hard disk device not connected to the extension board unit. Characteristic hard disk controller. 8. The hard disk control device according to claim 1, wherein the control interface of the main board unit has a serial interface for performing low-speed data communication and a parallel interface for performing high-speed data communication. Hard disk controller. 9. The hard disk control device according to claim 1, wherein a hard disk device is mounted instead of the plurality of hard disk devices connected to the expansion board, and the hard disk device is pseudo-recognized as the hard disk device with respect to the main board unit. A hard disk control device comprising a plurality of pseudo hard disk devices which are computers to be connected. 10. The hard disk control device according to claim 1, wherein the main board unit is connected to a computer, and the computer accesses a plurality of hard disk devices connected to the expansion board unit. apparatus. 11. The hard disk control device according to claim 10, wherein the same data is written to the plurality of hard disk devices, and when an error occurs in data read from an arbitrary hard disk device, data is read from another hard disk device. A hard disk control device characterized by being performed.