JP2015181043A - Memory, data processing method and memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory system capable of significantly reducing a system load related to a set operation frequently occurring in a full-text search system or the like and further capable of performing the set operation at a high speed.SOLUTION: A memory comprises: a first memory (KVS memory 14) stored with data and a key and a value being a group of the key and the value corresponding to the key; a second memory stored with the key and the value; a control circuit (CPU 11) controlling the first memory and the second memory; and a memory controller 13 connected between the control circuit and the first memory. The memory controller has a direct memory access (DMA) circuit, and the direct memory access circuit controls the first memory and the second memory with bypass of the control circuit.

Description

  Embodiments described herein relate generally to a memory, a data processing method, and a memory system accessed by a host system.

  In a general computer system equipped with a recent memory system, many data operations, particularly operations for handling a data set, frequently occur. For example, an operation of searching for data including two keywords A and B in a full-text search system or the like is nothing but obtaining a product set of a set of data including A and a set of data including B.

  In a general computer system, a memory system that manages data by address is the most widely used. When handling such data, data and addresses are managed on a one-to-one basis, and software processing based on a complicated algorithm is generally indispensable in order to handle a data set as described above.

  On the other hand, there are memory systems that manage data not by address but by its contents. However, although they are used for special purposes, they are rarely used for general computer systems from the viewpoint of cost and compatibility with existing systems.

  In a conventional computer system, when a data set operation is to be performed, complicated software processing is required due to restrictions on the memory system, and there are problems such as performance degradation and difficulty in handling.

JP 2005-209214 A Japanese Patent No. 4167359

  Provided are a memory, a data processing method, and a memory system that can remarkably reduce a system load related to a set operation that occurs frequently in a full-text search system or the like and that can perform a set operation at high speed.

  The memory of an embodiment includes a data, a first memory storing a key and a value corresponding to the key, a second memory storing the key and the value, the first memory, and the A control circuit for controlling a second memory; and a memory controller connected between the control circuit and the first memory. The memory controller has a direct memory access (DMA) circuit, and the direct memory access circuit controls the first memory and the second memory without going through the control circuit.

It is a figure which shows the 1st structural example of the KVS memory used for embodiment. It is a figure which shows the 2nd structural example of the KVS memory used for embodiment. It is a block diagram which shows the hardware constitutions of the memory system of 1st Embodiment. It is a figure which shows the structural example of the data area in the main memory of 1st Embodiment. It is a flowchart which shows the operation | movement of the AND operation in 1st Embodiment. It is a flowchart which shows the operation | movement of OR operation in 1st Embodiment. It is a flowchart which shows the operation | movement of NOT calculation in 1st Embodiment. It is a block diagram which shows the hardware constitutions of the memory system of the modification 1 in 1st Embodiment. It is a block diagram which shows the hardware constitutions of the memory system of the modification 2 in 1st Embodiment. It is a block diagram which shows the hardware constitutions of the memory system of the modification 3 in 1st Embodiment. It is a block diagram which shows the hardware constitutions of the memory system of 2nd Embodiment. It is a block diagram which shows the hardware constitutions of the memory system of the modification 1 in 2nd Embodiment. It is a block diagram which shows the hardware constitutions of the memory system of the modification 2 in 2nd Embodiment.

  In the following description, components having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

  A memory system (search memory) capable of a set operation according to the present embodiment includes a memory having at least one key-value store function (hereinafter referred to as KVS). KVS means a database management method in which a set of a key and a value is written and the value can be read by designating the key. In KVS, data is managed as key-value type data that is a set of key and value corresponding to key. When key is given as a search request, it is possible to output the value associated therewith. Here, a memory having such a KVS is hereinafter referred to as a KVS memory.

  Hereinafter, the KVS memory and its instructions will be described in detail.

  The KVS memory is a memory provided with at least KVS instructions such as GET, PUT, and DELETE in addition to normal memory access instructions, and the meaning of each instruction is as follows.

  (1) GET (key, value): If the element (value) is not specified (NULL), a data set corresponding to the key is obtained. When element (value) is specified, if value exists in the data set, value itself or TRUE is returned. If value does not exist in the data set, an empty set (NULL) or FALSE is returned. Even if there is no data set corresponding to key, an empty set (NULL) or FALSE is returned.

  (2) PUT (key, value): An element (value) is added to the data set corresponding to key. If the element already exists in the dataset, do nothing.

  (3) DELETE (key, value): Deletes an element (value) from the data set corresponding to key. Does nothing if the element does not exist in the dataset.

Hereinafter, a specific configuration example and operation example of the KVS memory will be shown.
FIG. 1 is a diagram illustrating a first configuration example of a KVS memory used in the embodiment.
As shown in the figure, for example, a memory controller 13 and a hash generator 16 are connected to the KVS memory 14. Further, the host system 100 is connected to the memory controller 13. The hash generator 16 has a function of a so-called hash function that converts arbitrary length data into a fixed length bit string. The host system 100 is, for example, a host system including a central processing unit (CPU) and a main memory.

  For the KVS memory 14, a general-purpose memory such as a DRAM is used. The KVS memory 14 is divided into at least two storage areas, a hash table area 14A and an actual data area 14B. Although there can be a plurality of these storage areas, the size of the hash table area 14A is larger than the size that the hash value (fixed length bit data) generated by the hash generator 16 can be expressed. The hash table area 14A is divided into an area that can store the real address of the key and an area that can store the real address of the value. The storage capacity of the hash table area 14A is not fixed, and can be varied (expanded or reduced) in response to a request based on the key-value store. Data is stored in the actual data area 14B.

  The memory controller 13 interprets the KVS instruction received from the host system 100 and performs the following operations on the KVS memory 14 and the hash generator 16.

  Consider a case where the key “animal” does not yet exist in the KVS memory 14. Here, when the memory controller 13 receives the commands PUT (animal, dog) and PUT (animal, cat) in order, the hash generator 16 generates hash values corresponding to each of animal, dog, and cat. Assume that these are sequentially fixed-length bit strings of 158, 98, and 188.

  Here, the contents of the address corresponding to the hash value in the hash table area 14A are examined, and it is checked whether or not the key “animal” has already been stored. Here, since it does not yet exist (because the value is 0), an area for storing each actual data is secured (1020, 1055, 1090), and these head addresses are stored in the key area of the hash table area 14A. Is done. In the secured areas (1020, 1055, 1090), actual data such as animals, dogs, and cats are stored.

  Further, in order to associate the key “animal” with the data set {dog, cat}, an area for each element is secured in the real data area 14B, and the start address (1100) is a value area corresponding to the animal in the hash table area 14A. Write to. Then, the elements (1055, 1090) in which the head addresses of the respective elements are arranged are stored in the actual data area 14B.

  Thus, a data set {dog, cat} corresponding to the key “animal” is created in the KVS memory 14. FIG. 1 shows the state in the KVS memory 14 at this time.

  Next, if the memory controller 13 receives an instruction “GET (animal, NULL)”, the contents (element actuality) of the value area (1100) written in the address (0158) that is the hash value of the animal in the hash table area 14A. The actual data is read from the top address of the data. That is, {dog, cat} is output to the host system 100.

  If the instruction is GET (animal, dog), the memory controller 13 does not output each element, but only outputs dog or TRUE only when there is an element that matches the second argument dog. Output to the system 100. If the instruction is GET (animal, lion), there is no matching element, so NULL or FALSE is output to the host system 100.

  Further, when the memory controller 13 receives the command DELETE (animal, dog), dog is deleted from the data set corresponding to animal. Specifically, each element starting from the address (1100) is examined, and the remainder (1090) excluding dog is written as a value. Alternatively, at this time, the elements excluding dog are sequentially written in the memory area newly reserved in the actual data area 14B, and finally the value area of the animal in the hash table area 14A is rewritten, and the original address (1100) There is also a way of opening up.

  In the case of DELETE, when the element of dog itself does not belong to a set other than animal, there is a case where an operation of releasing the memory used by the element of dog (garbage collection) may be accompanied.

  Here, if the instruction is GET (animal, NULL), {cat} is returned to the host system 100. Further, when the instruction is DELETE (animal, cat), the key area and the value area of the animal in the hash table area 14A are released, and the data set corresponding to the key “animal” disappears. That is, when the instruction is GET (animal, NULL), an empty set (NULL) is returned to the host system 100.

  In addition to the above, there are several implementation methods as examples of the configuration of the KVS memory. Specifically, a method of configuring the hash table area 14A using a content-addressable memory (CAM) in the configuration shown in FIG. 1 will be described below.

FIG. 2 is a diagram illustrating a second configuration example of the KVS memory used in the embodiment.
This configuration example includes a CAM-RAM 142 as a KVS memory, and a memory controller 13 that interprets a KVS command input from the host system 100 and controls the CAM-RAM 142 and other modules.

  The CAM-RAM 142 includes a CAM unit 142A as a table area and a RAM (random access memory) unit 142B as a data area. A general-purpose memory such as a DRAM or a NAND flash memory can be used for the RAM unit 142B. There are several types of associative memory (CAM part), but here the CAM part 142A is fixed when the input data (key) is included in the CAM in addition to normal reading and writing via the address. A type of CAM that returns long data (value) is used. In other words, the CAM unit 142A has a function of simultaneously performing parallel or coincidence comparison operations between the data and all stored data in response to the input of the data (key) and outputting the value of the matched stored data. .

  The CAM-RAM is a system in which an address is output by a content associative memory (CAM) and data is output by an addressed access RAM. In the CAM-RAM, since the key and value can be directly read and written without using the hash value, the hash generator 16 is not necessary as compared with the configuration example shown in FIG.

Next, the operation of the KVS instruction in the second configuration example will be described.
Consider a case where keys such as animal, dog, and cat do not yet exist in the CAM unit 142A. Here, when the memory controller 13 receives the commands PUT (animal, dog) and PUT (animal, cat) in order, it checks whether the key is already stored in the CAM unit 142A. Since the key does not exist yet, each key is stored in the CAM unit 142A. Then, the value of each element (dog, cat) in the CAM part (here, 1055 and 1090 of the head address) is secured in the RAM part 142B and stored as a set. Furthermore, the head address (1100) of this set is stored as the value of the key (animal) of the CAM unit 142A.

  At this time, the set can be stored in the CAM unit. However, since the CAM generally has a higher cost per bit than the RAM, it is better to use the above-described implementation method. FIG. 2 shows the state in the CAM-RAM 142 at this time.

  Next, assuming that the memory controller 13 receives an instruction “GET (animal, NULL)”, when the value 1100 corresponding to animal (key) of the CAM unit 142A is read as the address of the RAM unit 142B, the set {1055, 1090 } Can be read, and the key area obtained by rereading the set {1055, 1090} as the address of the CAM unit 142A, that is, {dog, cat} is output to the host system 100.

  If the instruction is GET (animal, dog), the memory controller 13 does not output each element, and only if there is an element that matches dog as the second argument, dog or TRUE Output to 100. If the instruction is GET (animal, lion), there is no matching element, so NULL or FALSE is output to the host system 100.

  Furthermore, when the memory controller 13 receives the command DELETE (animal, dog), dog is deleted from the data set corresponding to animal. Specifically, each element starting from the address (1100) is examined, and the remainder (1090) excluding dog is written as a value. Alternatively, at this time, elements excluding dog are sequentially written in a memory area newly secured in the RAM section, and finally the value area of the animal in the CAM section 142A is rewritten to release the original address (1100). There is also a way of.

  In the case of DELETE, when the element of dog itself does not belong to a set other than animal, there is a case where an operation of releasing the memory used by the element of dog (garbage collection) may be accompanied.

  Here, if the instruction is GET (animal, NULL), {cat} is returned to the host system 100. Further, when the instruction is DELETE (animal, cat), the key area and the value area of the animal in the CAM unit 142A are released, and the data set corresponding to the key “animal” disappears. That is, in the case of GET (animal, NULL), an empty set (NULL) is returned to the higher system 100.

[First Embodiment]
[1] Hardware Configuration First, the hardware configuration of the memory system of the first embodiment will be described.
FIG. 3 is a block diagram illustrating a hardware configuration of the memory system according to the first embodiment.
As shown in the figure, the memory system includes a CPU 11, a main memory 12, a memory controller 13, and a KVS memory 14. Further, the CPU 11, the main memory 12, and the memory controller 13 are connected by a bus 15.

  The CPU 11 controls the main memory 12, the memory controller 13, and the KVS memory 14 and performs a set operation described later. The memory controller 13 controls the KVS memory 14 and other memories (not shown). The memory controller 13 has a circuit having a direct memory access (DMA) function. If the DMA function is used, data transfer between the memory controller 13 and the main memory 12 can be directly controlled without using the CPU 11.

  The KVS memory 14 stores a data area as shown in FIG. 1 or FIG. The configuration and operation of the KVS memory 14 are as described with reference to FIG. 1 or FIG.

  FIG. 4 shows a configuration example of the data area in the main memory 12. The CPU 11 and the main memory 12 constitute a memory having a key-value store (KVS). For example, when the CPU 11 has a function of generating a hash value, the main memory 12 has a hash table area 12A and an actual data area 12B as shown in FIG. The main memory 12 stores data and instruction codes as main memory.

[2] Set Operation Next, a set operation in the memory system of the first embodiment will be described.

  Assume that two data sets, animal = {dog, tuna, cat} and fish = {porgy, tuna, salmon}, are stored in the KVS memory 14. Hereinafter, operations of the AND operation, the OR operation, and the NOT operation will be described.

(1) AND operation
FIG. 5 is a flowchart showing the operation of the AND operation in the first embodiment.
As a specific example, a process in the case of performing an operation called animal AND fish is shown. First, the CPU 11 issues a command “GET (animal, NULL)” to the KVS memory 14 via the memory controller 13 (step S1). Subsequently, in response to the GET (animal, NULL) instruction, the CPU 11 processes the data set output from the KVS memory 14 in the same manner as the operation of the KVS instruction described above (processing the hash function or the like in software), It is stored in the main memory 12 as an answer set. That is, the CPU 11 issues commands PUT (answer, dog), PUT (answer, tuna), and PUT (answer, cat) to the main memory 12. As a result, a set of answer = {dog, tuna, cat} is stored in the main memory 12 (step S2). Thereby, the main memory 12 functions as a memory having key-value type data. That is, the main memory 12 stores a pair of answer as a key and {dog, tuna, cat} as a value.

  Next, the CPU 11 checks whether each element in the answer set in the main memory 12 exists in the fish set in the KVS memory 14. Initially, the CPU 11 issues a command GET (fish, dog) to the KVS memory 14 (step S3). Since this return value is FALSE, the CPU 11 deletes the element dog in the answer set in the main memory 12. That is, the CPU 11 issues a DELETE (answer, dog) command to the main memory 12 (step S4).

  Subsequently, the CPU 11 determines whether or not the processing of all elements in the answer set in the main memory 12 has been completed (step S5). Here, since the processing of all elements in the answer set has not been completed, the process returns to step S3, and the processes after step S3 are repeated.

  The CPU 11 searches for the tuna from the fish set in the KVS memory 14. That is, the CPU 11 issues a command GET (fish, tuna) to the KVS memory 14 (step S3). Then, since this return value is TRUE, it proceeds to the next.

  Similarly, for the cat, the CPU 11 searches for the cat from the fish set in the KVS memory 14. That is, the CPU 11 issues a command “GET (fish, cat)” to the KVS memory 14 (step S3). Then, since this return value is FALSE, the CPU 11 deletes the element cat in the answer set in the main memory 12. That is, the CPU 11 issues a DELETE (answer, cat) command to the main memory 12 (step S4).

  When processing of all elements in the answer set is completed in step S5, the answer set in the main memory 12 is answer = {tuna} as a result, resulting in an AND operation solution (step S6).

  If a solution set with a name different from answer is prepared, a plurality of AND operations can be performed simultaneously.

(2) OR operation
FIG. 6 is a flowchart showing the operation of the OR operation in the first embodiment.
As a specific example, a process for performing an operation called animal OR fish is shown. First, the CPU 11 issues a command “GET (animal, NULL)” to the KVS memory 14 via the memory controller 13 (step S11). Subsequently, in response to a GET (animal, NULL) instruction, the CPU 11 stores the data set output from the KVS memory 14 in the main memory 12 as an answer set. That is, the CPU 11 issues commands PUT (answer, dog), PUT (answer, tuna), and PUT (answer, cat) to the main memory 12. As a result, a set answer = {dog, tuna, cat} is stored in the main memory 12 (step S12). Thereby, the main memory 12 functions as a memory having key-value type data. That is, the main memory 12 stores a pair of answer as a key and {dog, tuna, cat} as a value.

  Next, the CPU 11 checks whether each element in the fish set in the KVS memory 14 exists in the answer set in the main memory 12. Initially, the CPU 11 issues a command “GET (answer, porgy)” to the main memory 12 (step S13). Since this return value is FALSE, the CPU 11 puts porgy into the answer set in the main memory 12. That is, the CPU 11 issues a PUT (answer, porgy) command to the main memory 12 (step S14).

  Subsequently, the CPU 11 determines whether the processing of all elements in the fish set in the KVS memory 14 has been completed (step S15). Here, since the processing of all the elements in the fish set has not been completed, the process returns to step S13, and the processes after step S13 are repeated.

  The CPU 11 checks whether the tuna in the fish set in the KVS memory 14 exists in the answer set in the main memory 12. That is, the CPU 11 issues a command GET (answer, tuna) to the main memory 12 (step S13). Then, since the return value is TRUE, it proceeds to the next.

  Similarly for salmon, the CPU 11 checks whether or not salmon in the fish set exists in the answer set in the main memory 12. That is, the CPU 11 issues a command “GET (answer, salmon)” to the main memory 12 (step S15). Then, since this return value is FALSE, the CPU 11 puts salmon in the answer set in the main memory 12. That is, the CPU 11 issues a PUT (answer, salmon) command to the main memory 12 (step S14).

  In step S15, when processing of all elements in the fish set is completed, the answer set in the main memory 12 is answer = {dog, tuna, cat, porgy, salmon}, which is the solution of the OR operation. (Step S16).

  If a solution set with a name different from answer is prepared, a plurality of OR operations can be performed simultaneously.

(3) NOT operation
FIG. 7 is a flowchart showing the NOT calculation operation in the first embodiment.
As a specific example, a process for performing an operation called animal NOT fish is shown. First, the CPU 11 issues a command “GET (animal, NULL)” to the KVS memory 14 via the memory controller 13 (step S21). Subsequently, in response to a GET (animal, NULL) instruction, the CPU 11 stores the data set output from the KVS memory 14 in the main memory 12 as an answer set. That is, the CPU 11 issues commands PUT (answer, dog), PUT (answer, tuna), and PUT (answer, cat) to the main memory 12. As a result, the set answer = {dog, tuna, cat} is stored in the main memory 12 (step S22). Thereby, the main memory 12 functions as a memory having key-value type data. That is, the main memory 12 stores a pair of answer as a key and {dog, tuna, cat} as a value.

  Next, the CPU 11 deletes each element in the fish set in the KVS memory 14 from the answer set in the main memory 12. Initially, the CPU 11 issues a command DELETE (answer, porgy) to the main memory 12 (step S23).

  Subsequently, the CPU 11 determines whether or not processing of all elements in the fish set in the KVS memory 14 has been completed (step S24). Here, since the processing of all the elements in the fish set has not been completed, the process returns to step S23, and the processes after step S23 are repeated.

  Similarly, the CPU 11 deletes tuna and salmon in the fish set in the KVS memory 14 from the answer set in the main memory 12 (step S23).

  When processing of all elements in the fish set is completed in step S24, the answer set in the main memory 12 is answer = {dog, cat} as a result, which is a NOT calculation solution (step S25).

  If a solution set with a name different from answer is prepared, a plurality of NOT operations can be performed simultaneously.

  Further, all the operations performed by the CPU 11 described above can be executed by the direct memory access (DMA) function of the memory controller 13. By performing all the operations performed by the CPU 11 using the DMA function of the memory controller 13, the above-described set operation can be performed without imposing a load on the CPU 11.

[3] Modification 1
FIG. 8 is a block diagram illustrating a hardware configuration of a memory system according to Modification 1 of the first embodiment.

  As shown in the figure, the first modification has a configuration including a hash generator 16 in the memory system of the first embodiment shown in FIG. The hash generator 16 has a function of a so-called hash function that converts arbitrary length data into a fixed length bit string. Here, the hash generator 16 generates an address at which key-value type data is stored in response to input of data (key).

  The KVS memory 14 in FIG. 8 has the same configuration as the KVS memory 14 shown in FIG. The main memory 12 has the same configuration as the main memory 12 shown in FIG. Therefore, the detailed configuration and operation of the KVS memory 14 and the main memory 12 in FIG. 8 are omitted here.

  The operation of the set operation in the first modification is the same as the operation in the first embodiment. In Modification 1, by providing the hash generator 16, it is possible to reduce the load on the CPU 11 during execution of the set operation. Other configurations and effects are the same as those of the first embodiment described above.

[4] Modification 2
FIG. 9 is a block diagram illustrating a hardware configuration of a memory system according to Modification 2 of the first embodiment.

  As illustrated, the second modification includes the hash generator 16 in the memory system according to the first embodiment illustrated in FIG. 3 and uses a DRAM 141 as the KVS memory. Further, a NAND flash memory 17 is provided as a memory device connected to the memory controller 13.

  The DRAM 141 in FIG. 9 has the same configuration as the KVS memory 14 shown in FIG. The main memory 12 has the same configuration as the main memory 12 shown in FIG. Therefore, the detailed configuration and operation of the DRAM 141 and the main memory 12 in FIG. 9 are omitted here.

  In the second modification, the DRAM 141 is used as the KVS memory 14 in the first embodiment, and the operation of the set operation in the second modification is the same as the operation in the first embodiment. Furthermore, by providing the hash generator 16, it is possible to reduce the load on the CPU 11 during execution of the set operation. Other configurations and effects are the same as those of the first embodiment described above.

[5] Modification 3
FIG. 10 is a block diagram illustrating a hardware configuration of a memory system according to Modification 3 of the first embodiment.

  As shown in the figure, the third modification uses a CAM-RAM 142 as a KVS memory in the memory system of the first embodiment shown in FIG. Further, a NAND flash memory 17 is provided as a memory device connected to the memory controller 13.

  The CAM-RAM 142 in FIG. 10 has the same configuration as the CAM-RAM 142 shown in FIG. The main memory 12 has the same configuration as the main memory 12 shown in FIG. Therefore, the detailed configuration and operation of the CAM-RAM 142 and the main memory 12 shown in FIG.

  In the third modification, the CAM-RAM 142 is used as the KVS memory 14 in the first embodiment, and the operation of the set operation in the third modification is the same as the operation in the first embodiment. Furthermore, by providing the CAM-RAM 142, it is possible to reduce the load on the CPU 11 when the set operation is executed. Other configurations and effects are the same as those of the first embodiment described above.

[Second Embodiment]
[1] Hardware Configuration A hardware configuration of the memory system according to the second embodiment will be described.
FIG. 11 is a block diagram illustrating a hardware configuration of the memory system according to the second embodiment.
As shown in the figure, the memory system includes a CPU 11, a main memory 12, a memory controller 13, a first KVS memory 24, and a second KVS memory 34. Further, the CPU 11, the main memory 12, and the memory controller 13 are connected by a bus 15.

  The CPU 11 controls the main memory 12, the memory controller 13, and the first and second KVS memories 24 and 34, and performs a set operation described later. The memory controller 13 controls the KVS memories 24 and 34 and other memories (not shown). The memory controller 13 has a circuit having a direct memory access (DMA) function. If the DMA function is used, data transfer between the memory controller 13 and the main memory 12 can be directly controlled without using the CPU 11.

  The first and second KVS memories 24 and 34 store data areas as shown in FIG. The configurations and operations of the KVS memories 24 and 34 are the same as those described with reference to FIG. 1 or FIG.

[2] Set Operation Next, a set operation in the memory system of the second embodiment will be described.

  In the set operation in the second embodiment, the CPU 11 is replaced with the memory controller 13 in the set operation in the first embodiment described above, the KVS memory 14 is replaced with the first KVS memory 24, and the main memory 12 is replaced with the second. The KVS memory 34 is replaced.

  Now, it is assumed that two data sets of animal = {dog, tuna, cat} and fish = {porgy, tuna, salmon} are stored in the first KVS memory 24. The operations of the AND operation, OR operation, and NOT operation will be described below with reference to FIGS.

(1) AND operation
As a specific example, a process in the case of performing an operation called animal AND fish is shown. First, the memory controller 13 issues a command GET (animal, NULL) to the first KVS memory 24 (step S1). Subsequently, in response to a GET (animal, NULL) instruction, the memory controller 13 causes the second KVS memory 34 to store the data set output from the first KVS memory 24 as an answer set. That is, the set answer = {dog, tuna, cat} is stored in the second KVS memory 34 (step S2).

  Next, the memory controller 13 checks whether each element in the answer set in the second KVS memory 34 exists in the fish set in the first KVS memory 24. Initially, the memory controller 13 issues a command GET (fish, dog) to the first KVS memory 24 (step S3). Since this return value is FALSE, the memory controller 13 deletes the element dog in the answer set in the second KVS memory 34 (step S4).

  Subsequently, the memory controller 13 determines whether the processing of all elements in the answer set in the second KVS memory 34 has been completed (step S5). Here, since the processing of all elements in the answer set has not been completed, the process returns to step S3, and the processes after step S3 are repeated.

  The memory controller 13 searches for the tuna from the fish set in the first KVS memory 24. That is, the memory controller 13 issues a command “GET (fish, tuna)” to the first KVS memory 24 (step S3). Then, since this return value is TRUE, it proceeds to the next.

  Similarly, for the cat, the memory controller 13 searches for the cat from the fish set in the first KVS memory 24. That is, the memory controller 13 issues a command “GET (fish, cat)” to the first KVS memory 24 (step S3). Then, since this return value is FALSE, the memory controller 13 deletes the element cat in the answer set in the second KVS memory 34 (step S4).

  When processing of all elements in the answer set is completed in step S5, the answer set in the second KVS memory 34 is answer = {tuna} as a result, which is the solution of the AND operation (step S6).

(2) OR operation
As a specific example, a process for performing an operation called animal OR fish is shown. First, the memory controller 13 issues an instruction “GET (animal, NULL)” to the first KVS memory 24 (step S11). Subsequently, in response to a GET (animal, NULL) instruction, the memory controller 13 causes the second KVS memory 34 to store the data set output from the first KVS memory 24 as an answer set. That is, the set answer = {dog, tuna, cat} is stored in the second KVS memory 34 (step S12).

  Next, the memory controller 13 checks whether each element in the fish set in the first KVS memory 24 exists in the answer set in the second KVS memory 34. Initially, the memory controller 13 issues a command “GET (answer, porgy)” to the second KVS memory 34 (step S13). Since this return value is FALSE, the memory controller 13 puts porgy into the answer set in the second KVS memory 34 (step S14).

  Subsequently, the memory controller 13 determines whether the processing of all elements in the fish set in the first KVS memory 24 has been completed (step S15). Here, since the processing of all the elements in the fish set has not been completed, the process returns to step S13, and the processes after step S13 are repeated.

  The memory controller 13 checks whether tuna in the fish set in the first KVS memory 24 exists in the answer set in the second KVS memory 34. That is, the memory controller 13 issues a command “GET (answer, tuna)” to the second KVS memory 34 (step S13). Then, since the return value is TRUE, it proceeds to the next.

  Similarly for salmon, the memory controller 13 checks whether the salmon in the fish set exists in the answer set in the second KVS memory 34. That is, the memory controller 13 issues a command “GET (answer, salmon)” to the second KVS memory 34 (step S15). Then, since this return value is FALSE, the memory controller 13 puts salmon in the answer set in the second KVS memory 34 (step S14).

  In step S15, when all elements in the fish set have been processed, the answer set in the second KVS memory 34 is answer = {dog, tuna, cat, porgy, salmon}, and the OR operation is performed. A solution is obtained (step S16).

(3) NOT operation
As a specific example, a process for performing an operation called animal NOT fish is shown. First, the memory controller 13 issues a command “GET (animal, NULL)” to the first KVS memory 24 (step S21). Subsequently, in response to a GET (animal, NULL) instruction, the memory controller 13 causes the second KVS memory 34 to store the data set output from the first KVS memory 24 as an answer set. That is, the set answer = {dog, tuna, cat} is stored in the second KVS memory 34 (step S22).

  Next, the memory controller 13 deletes each element in the fish set in the first KVS memory 24 from the answer set in the second KVS memory 34. Initially, the memory controller 13 issues a command DELETE (answer, porgy) to the second KVS memory 34 (step S23).

  Subsequently, the memory controller 13 determines whether the processing of all elements in the fish set in the first KVS memory 24 has been completed (step S24). Here, since the processing of all the elements in the fish set has not been completed, the process returns to step S23, and the processes after step S23 are repeated.

  Similarly, the memory controller 13 deletes tuna and salmon in the fish set in the first KVS memory 24 from the answer set in the second KVS memory 34 (step S23).

  When the processing of all elements in the fish set is completed in step S24, the answer set in the second KVS memory 34 is answer = {dog, cat} as a result, which is the solution of the NOT operation (step S25). ).

  Further, all the operations performed by the memory controller 13 described above can be executed by the direct memory access (DMA) function of the memory controller 13. By performing all the operations performed by the memory controller 13 using the DMA function of the memory controller 13, it is possible to perform the aforementioned set operation without imposing a load on the memory controller 13.

[3] Modification 1
FIG. 12 is a block diagram illustrating a hardware configuration of a memory system according to Modification 1 of the second embodiment.

  As shown in the figure, the first modification includes the hash generator 16 in the memory system of the second embodiment shown in FIG. 11, and uses a DRAM 241 and a CAM-RAM type NAND flash memory 341 as the KVS memory.

  The DRAM 241 in FIG. 12 has the same configuration as the KVS memory 14 shown in FIG. Further, the CAM-RAM type NAND flash memory 341 has the same configuration as the CAM-RAM 142 shown in FIG. Therefore, the detailed configuration and operation of the DRAM 241 and the CAM-RAM type NAND flash memory 341 in FIG. 12 are omitted here.

  The operation of the set operation in the first modification is the same as the operation in the second embodiment. Furthermore, by providing the hash generator 16 and the CAM-RAM type NAND flash memory 341, it is possible to reduce the load on the CPU 11 during execution of the set operation. Other configurations and effects are the same as those of the second embodiment described above.

[4] Modification 2
FIG. 13 is a block diagram illustrating a hardware configuration of a memory system according to Modification 2 of the second embodiment.

  As shown in the figure, the second modification uses a CAM-RAM 242 and a CAM-RAM type NAND flash memory 341 as the KVS memory in the memory system of the second embodiment shown in FIG.

  The CAM-RAM 242 and the CAM-RAM type memory 341 in FIG. 13 have the same configuration as the CAM-RAM 142 shown in FIG. Therefore, the detailed configuration and operation of the CAM-RAM 242 and the CAM-RAM type memory 341 in FIG. 12 are omitted here.

  The operation of the set operation in the second modification is the same as the operation in the second embodiment. Furthermore, by providing the CAM-RAM 242 and the CAM-RAM type NAND flash memory 341, it is possible to reduce the load on the CPU 11 when the set operation is executed. Other configurations and effects are the same as those of the second embodiment described above.

  According to the embodiment, it is possible to provide a memory system that can remarkably reduce a system load related to a set operation that frequently occurs in a full-text search system or the like, and can perform a set operation at high speed.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 11 ... CPU, 12 ... Main memory, 12A ... Hash table area, 12B ... Real data area, 13 ... Memory controller, 14 ... KVS memory, 14A ... Hash table area, 14B ... Real data area, 15 ... Bus, 16 ... Hash Generator: 17 ... NAND flash memory, 24 ... first KVS memory, 34 ... second KVS memory, 100 ... host system, 141 ... DRAM, 142 ... CAM-RAM, 142A ... CAM unit, 142B ... RAM unit, 241 ... DRAM, 242 ... CAM-RAM, 341 ... CAM-RAM type NAND flash memory.

Claims (15)

A first memory storing data, a key and a value corresponding to the key;
A second memory storing the key and the value;
A control circuit for controlling the first memory and the second memory;
A memory controller connected between the control circuit and the first memory;
The memory controller includes a direct memory access (DMA) circuit;
The direct memory access circuit is a memory that controls the first memory and the second memory without going through the control circuit. The key and the value have a first address and a first value corresponding to the first key and the first key, and the first key and the first value are stored in the first address, and a second address Is stored in the first value,
The memory according to claim 1, wherein a second value is obtained by referring to a storage location in the first memory designated by the second address.   The memory of claim 2, further comprising: a hash generator that generates the first address in which the first key and the first value are stored by a hash function with respect to the input of the first key.   The memory according to claim 1, wherein the first memory is a DRAM. The first memory compares the first key with the data stored in the first memory with respect to the input of the first key, and obtains a third address where the matched data is stored. Content-addressable memory (CAM) to output,
The memory according to claim 1, further comprising a RAM that performs writing and reading according to the designation of the third address.   The memory according to claim 1, wherein the second memory is a main memory controlled by the control circuit.   The memory according to claim 6, wherein the main memory is a DRAM. The second memory compares the first key with the data stored in the second memory in response to the input of the first key, and obtains a third address where the matched data is stored. Content associative memory (CAM) to output,
The memory according to claim 1, further comprising a RAM that performs writing and reading according to the designation of the third address.   The memory according to claim 8, wherein the second memory is a NAND flash memory.   10. The memory according to claim 1, wherein the control circuit varies a storage capacity of the key and the value stored in the first memory in response to a request based on the key and the value.   The memory according to claim 1, wherein the control circuit is a CPU connected to the first and second memories via a bus.   The memory according to claim 1, wherein the set operation performed by the control circuit is any one of AND, OR, and NOT. A first memory storing data, a key, and a value corresponding to the key; a second memory storing the key and the value; and controlling the first memory and the second memory In a data processing method of a memory system having a control circuit,
A data processing method for controlling the first memory and the second memory by a direct memory access (DMA) circuit without going through the control circuit. A first memory storing data, a key and a value corresponding to the key;
A second memory storing the key and the value;
A control circuit for controlling the first memory and the second memory;
A memory controller connected between the control circuit and the first memory;
The memory controller includes a direct memory access (DMA) circuit;
The direct memory access circuit controls the first memory and the second memory without going through the control circuit.   The memory system according to claim 14, further comprising a host system accessible to the memory system.