JPS5960658A - Semiconductor storage device provided with logical function - Google Patents

Abstract

PURPOSE:To lighten the load of a CPU side and reduce the processing time, by installing a logical operation circuit and logic controller to a memory side and giving a simple operational function which can be executed at one memory cycle to the memory side. CONSTITUTION:Data A read out at the preceding time from a memory cell array 21 are stored in a data register 29. A logical operation circuit 30 has a simple operational function which can be executed by 1-step instruction. The data inputs are the preceding data A from the register 29, current data B read out from the memory cell array 21, and external data C given from a CPU1 side. A logic controller 31 gives an instruction that what kind of operation must be performed on which data to the logical operation circuit 30 depending on the content of a logic bus between a memory and the CPU. The operated result of the circuit 30 is written in the memory cell array 21 through a write buffer 28, I/O gate 23.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a novel semiconductor memory device having a logical operation function.

Background of the Technology Conventional semiconductor storage devices (hereinafter simply referred to as memories) have only the function of storing information. For this reason, even when performing simple logical operations such as AND and OR, ■ Sending information from memory to the CPU, ■ Performing calculations on the CPU, ■
It is necessary to write the result into memory.

Prior Art and Problems Figure 1 is a block diagram of a CPLJ system using conventional memory, where 1 is a CPU (central processing unit), 2 is one of many memories (here refers to one chip of memory), 3
are read and write control lines, 4 is an address bus, and 5 is a data bus. In this system, the stored data is AND,
Even when performing simple logical operations such as OR, an address is given from the CPU through the memory 2 head address 4, a read command is issued through the control line 3, the data at the corresponding address is sold 8, and it is transferred from the ■/○ boat to the table. - It is necessary to import the data into the CPU via the Thanos 5, perform the necessary logical operations, and then send the result to the memory 2 via the data bus 5 and write it by giving a write command via the control line 3. . The CPU must be involved in all three operations (reading from memory, performance, and loading into memory). This also happens in memory 2.
This is because it simply memorizes and has no arithmetic functions.

FIG. 2 shows the internal configuration of a 1-nap memory 2, in which 21 is a cell array in which a large number of memory cells (dynamic or static cells) are arranged in a matrix, 22 is a row (ROW) decoder, 23 is an input/output gate, 24 is a column decoder, 25 is an address buffer that takes in the address from address designation 4 in FIG. 27 is an output B node interposed between the external data bus 5 connected to the I10 port and the internal data bus 5a connected to the I10 gate 23, and 28 is a recessed buffer used during writing.

When an address from the CPUI is given to the address buffer 25, its upper and lower parts are multiplied by 4+1 and sent to the decoder 2.
2.24 and the corresponding cell is selected. At the time of reading, the take of the corresponding cell is output to the data bus 5 through the I10 gate 23, the take hash 5a, the output buffer sofa 27, and the I10 port, and is taken into the CPUI. During writing, the take input through the I10 port is sent to the write buffer 28, data bus 5a, and I10 cable 1-23.
is transferred to the corresponding cell through. At this time as well, the required address is of course given to the address buffer 25, and reading and writing are switched by selecting the buffers 27 and 28 by the controller I-roller 2G.

Purpose of the Invention The present invention aims to reduce the burden on the CP (J side) and shorten the processing time by equipping the memory side with a simple calculation function that can be executed in one memory cycle. be.

Structure of the Invention The present invention provides a semiconductor memory device in which a cell array in which a large number of memory cells are arranged in a matrix and peripheral circuits necessary for writing and reading data to the cell array are integrated into one chip. It includes a logic circuit having a logic function, an I/O controller that instructs the logic circuit to perform a logic operation using data read from the cell array or data given from the outside, and By simultaneously providing the address necessary for selecting the cell array, the data necessary for the operation of the logic circuit, and the information necessary for the controller I/roller to control the logic circuit, the cell array can be read in one memory cycle. It is characterized in that the calculation result of the logic circuit is written into the addressed cell or the Ltl calculation result is read out.This will be explained in detail below with reference to the illustrated embodiment. .

Embodiment of the Invention FIGS. 3 and 4 are configuration diagrams showing an embodiment of the present invention, in which the same parts as those described above are given the same reference numerals.

Since the memory 2 in this example has the configuration shown in FIG.
It is necessary to newly install a logic hash 6 between the two as shown in Fig. 3. Configuration 4.1 added in FIG. 4: Data register 29, logic circuit 30, and logic controller 31 within the broken line frame. Data register 29 stores data A that was previously read from cell array 21 . The logic circuit 30 is equipped with a simple arithmetic function (described later) that can be executed by a one-step instruction, and its data input is the previous data A from the register 29, the current take B newly read from the cell array 21, and the CPU This is external data C given from the side. The logic circuit 3 is controlled by the contents of the logic hash 6 in the long controller 31.
0, an instruction is given as to which data and which calculation should be performed.

The result of the operation by the logic circuit 30 is then written to the cell array 21 through the write buffer 28 and I10 gate j23.

Memory 2 in this example is connected to logic bus 6 with 5 HI
It is equipped with socket terminals 1-I-L 5,
, 1 to 1.3 together with 11 (high) and L (low) indicate the various logics in Table 1, and L4. L5 is H,1,
It is assumed that the data types in Table 2 are specified by the combination of , U. However, the logic type No. 9 in Table 1 is necessary for threading operation with the logic circuit 30 being passed through.

Table 1 Table 2 Therefore, for example, L 1 = I-, I-2 = 1. -3=L
, a=L5-H, the instruction content is to take the ant (ANIT) between the data B read this time from the cell array 21 and the data C given from the CPUI. At this time, the calculation result is written this time to the same successive address of data B, so that all operations are completed in one memory cycle. If you do this like this, the CPU
I simply gives the address of the cell to be selected to the memory 2, the external data C8, and the instructions for the logical operation contents at the same time, and from then on, other processing can be performed, so the processing time is reduced to 1/3. be shortened. Furthermore, cell array 2
1 to current data B) c not read L a =I-,L
In the case of 5-H, the address given from the CPUI specifies the cell into which the operation result is written. Also, when the current data B is successively output from the cell array 21 and calculated by /i1, the indicator from the CP river is only written (write), the output buffer sofa 27 is turned off, and the write buffer 28 is turned on. . Therefore, data I3 is successively written to the cell array 21 in the first half of one memory cycle, and the calculation result is written in the second half. In this case, there is a time delay before the write buffer 28 is activated, during which time the write buffer 28 is activated.

Since the property that the data B is taken into the circuit 3o once is utilized, there is no need for particular timing control. Furthermore, since the data register 29 is like a register, the previous data 8 can be given to the circuit 30 one by one until its contents change to the current data B. 1. The circuit 30 is a collection of various cables 1 and cheeks, and its path is from controller 1 to roller 3.
The output is changed to the desired /Jii force. In this case, if a renostar is also provided in the logic circuit 30 and the controller 31 decodes the command received from CI) tJ 1 and gives multiple step instructions to the logic circuit 30, more complex calculations can be performed.

FIG. 5 shows another embodiment of the present invention, which differs from FIG. 4 in that the data input to the output sofa 27 also passes through the logic circuit 30. In the illustrated example, the I10 terminal is separated into In and Qut, but this can be made common by providing an Ilo control terminal (this is already the case in the Guinami Soku memory). The memory 2 of this example can utilize the calculation function of the logic circuit 30 not only in the write mode but also in the read mode. Since the write buffer 28 is off in the cell array]-mode, the operation result cannot be written to the cell array. However, since the calculation results can be given to other memories from the output sofa 27, data (calculation results) can be exchanged between the memories without going through the CPUI.

The data register DATA REG 29 shown in this embodiment and FIGS. 4 and 5 is not necessarily a necessary function of the present invention. In the data to be calculated, L
In the case where a=Ls=H, the /iM calculation is performed between the data read this time and the external data. With this function alone, calculation results can be written or read in one memory cycle without using the CPU, and the main purpose of the present invention can be achieved.

Effects of the Invention As described above, according to the present invention, three steps (reet, operation,
Since +1 only requires one step operation, there is an advantage that the speed of the entire system is tripled. Therefore, it is extremely useful for systems that store a large amount of data in a memory and process and update the data within a short period of time, such as image processing by a computer.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a system using conventional memory;
U2JD, 1 is a configuration diagram of a conventional memory, FIG. 83 is a configuration diagram of a system using a memory related to the present invention, and FIGS. 4 and 5 are memory configuration diagrams showing different embodiments of the present invention. In the figure, 1 is the central processing unit (CPtJ), 2 is the memory,
3 is read, write 1 to control line, 4 is address bus, 5 is data bus, 6 is logic bus, 21 is cell array, 2
2 to 28 are peripheral circuits, 29 is a data processor, 30 is a logic circuit, and 3X is a logic controller. Applicant Fujitsu Limited Representative Patent Attorney Minoru Aoyagi

Claims (1)

[Claims] In a semiconductor memory device in which a cell array in which a large number of memory cells are arranged in a matrix and peripheral circuits necessary for writing and outputting data to the cell array are integrated into one chip, a logic device having various logic functions, a logic controller that instructs the logic circuit to perform a logical operation using data read from the cell array or data given from the outside, and a logic controller that instructs the logic circuit to perform a logical operation using data read from the cell array or data given from the outside, address, the data necessary for the operation of the logic circuit, and the logic circuit (
・The roller controls the logic circuit. ・By simultaneously giving the necessary information, the operation result of the logic circuit is written to the addressed cell in the cell array in one memory cycle, or the operation result is written to the addressed cell in the cell array. 1. A semiconductor memory device having a logic function, characterized in that a semiconductor memory device is configured to operate without reading data.