JPS63188883A - Storage device - Google Patents

Abstract

PURPOSE:To quicken stack operation being last write and first read by providing an address generating circuit in the inside of a memory. CONSTITUTION:Suppose that an internal address generated by an internal address generating circuit in the inside of a memory 1 is A1, the memory 1 receiving a chip selection signal CS from a CPU opens a chip selection transfer gate 15. Since a write signal WR is given in this case, all write enable transfer gates 11 are opened. Then the signal A1 opens a write transfer gate 12 through the gate 11 and the content of a data bus 3 is written in each storage element 10 of the storage circuit 7. Thus, the address of the circuit 16 is added by the circuit 16. Then in case of readout, a signal A2 is selected, a read enable transfer gate 13 is opened by the signal CS and read signal RD, a transfer gate 14 is opened and the content of the element 10 in the circuit 7 is read to the bus 3. The internal address is subtracted at the same time.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a memory device comprising a semiconductor integrated circuit.
In particular, the present invention relates to a storage device that speeds up stack operations in a central processing unit.

[Conventional technology]

FIG. 5 is a connection diagram of a conventional central processing unit (hereinafter referred to as CPU) and a storage device (hereinafter referred to as memory) when performing a stack operation. In the figure, 1 is a memory made of a semiconductor integrated circuit, 2 is a CPU, and 3
is the data bus between CPU2 and one memory, 4 is the C
The control signal line on which the control signal output by PU2 is carried, 18 is C
This is an address bus on which address data output from PU2 is carried.

Next, the operation will be explained.

First, stack operation will be explained. Here, the stack operation is a storage method performed by reading the post-write destination when saving an address or data held by the CPU 2. In this case, the CPU 2 remembers the last stored address. I have to keep it.

When the CPU 2 performs a stack operation, since there is a stack area in the real memory space, the same operation as normal data transfer between memories is performed. To explain this using the timing diagram of FIG. 6, first, as shown in FIG. 6, an address signal is output to one memory. This clock is assumed to be T1 as shown in the figure (Jl). During this TlO period, the address signal is decoded and the same figure (
g), the integrated circuit selection signal (
A memory selection signal (hereinafter referred to as a chip selection signal) (C8) is activated to select a memory. At the next clock (T2), the same figure (
cl, as shown in (e), the CPU 2 sends a control signal (write signal (WR) for writing, read signal (RD) for reading) to the memory to indicate what kind of operation to perform. The operation ends at the next clock (T3). Figure (d) shows the data output during reading;
f) shows data input during writing.

Further, all control signals are shown as "H" active.

[Problem that the invention seeks to solve]

The stack area of conventional CPUs was located in normal memory space, so the time from address output to data transfer could not be made any shorter than with other memories.
Since U must have a circuit for storing the last storage address, there is a problem in that a large amount of execution time is required when executing a program that involves many stack operations.

This invention was made to solve the above-mentioned problems, and it enables the CPU to perform stack operations without outputting addresses, and also eliminates the stack area from the real memory space. ), the purpose is to provide a memory that can speed up the stack operation of the CPU.

[Means for solving problems]

A storage device (memory) according to the present invention is provided with an internal address generation circuit that generates an internal address signal at the same time as writing or reading is performed.

[Effect]

The internal address generation circuit according to the present invention generates an address signal in which 1 is added in writing, and an address signal in which 1 is subtracted in reading. Furthermore, in the case of continuous write or read operations several times, constant write and read operations are possible by adding or subtracting an internal address to an external synchronization signal (clock signal).

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. Second
In the figure, 1 is a storage device with internal addresses (hereinafter referred to as memory), 2 is a CPU, 3 is a data bus between CPU 2 and memory 1, and 4 is a control signal line on which control signals output by the CPU are carried. It is. FIG. 3 is a timing chart showing the operation.

Further, FIG. 1 shows the internal structure of the memory 1. As shown in FIG.

In the figure, 5 is a main memory circuit column, 6 to 9 are first to nth memory circuits in the memory circuit column 5, and 10 is a memory circuit 6 to 9.
11 is a write permission transfer gate that enables writing, and 12 is a write permission transfer gate that transfers the contents of the data bus 3 to a certain storage element when the conditions of this write permission transfer gate and the internal address are met. Write transfer gate to write to 10, 13
14 is a read permission transformer 7ar gate that enables reading, and 14 is a read transfer gate that reads data from the storage element 10 onto the data bus 3 when the conditions of this read permission transfer gate and the internal address are met; 15 16 is an internal address generation circuit that automatically generates an internal address; 17 is a clock connected to this internal address generation circuit 16; 16 is an internal address generation circuit that automatically generates an internal address; This is a signal input terminal.

Next, the operation will be explained.

In the above configuration, when performing a stack operation, the CPU 2 stores data to be saved in a certain memory (only C), and uses a control signal that functions as a selection signal for only that memory. It is assumed that a chip selection signal (CS) is provided.

As shown in FIG. 3(b), this chip selection signal is combined with other control signals (read signals (
RD) and write signal (WR)).

When this CPU2 performs stack operation, memory 1
Memory 1 is automatically generated internally.
Since the address has been selected in advance, the CPU 2 does not need to output the address. Therefore, TI in FIG. 6 is omitted.

Furthermore, if the memory 1 operates at a sufficiently high speed, T2 in FIG. 6 can be omitted, and in the end, FIG. 6 becomes like the timing diagram shown in FIG. 3. In other words, the same figure (a)
The stack operation is completed only with the clock T3 shown in FIG.

Although FIG. 3 shows the case where the read/write operation is executed only once, when the read/write operation is executed continuously, the address is automatically added or subtracted by the internal address generation circuit 16 in the memory 1 every clock. Therefore, in the case of writing, the CPU 2 may input data every one clock, and in the case of reading, the data may be output from the memory 1 every one clock.

Next, the internal operation of the memory 1 will be described in detail with reference to FIG. 1, assuming that a read operation is performed after a write operation. Now, in Figure 3, the internal address shown in ) is A
Suppose it was I. In this case, reading is performed from the first memory circuit 6, and writing is performed from the second memory circuit T. First, the memory 1 receives a chip selection signal (C8), which is a control signal indicating that a stack operation is to be performed, from the CPU 2, and then transmits a write signal (WR) and a read signal (RD) to the inside of the memory 1. To enable this, the chip selection transfer gate 15 is opened.

At that time, since the write signal (WR) has already been output, all write permission transfer gates 11 are challenged. Now, since A1 is an internal address, the signal of A1 opens the write transfer gate 12 through the transfer gate, and the contents of the data bus 3 are transferred to the second memory circuit 7 as shown in FIG. 3(f). The data is written to each memory element 10. At the same time, the address of the internal address generation circuit 16 is
is added to complete the write operation. after that,
When performing a read operation, A2 is selected, the read permission transfer gate 13 is opened by the chip selection signal (CS) and the read signal (RD), and the read transfer gate 13 of the second memory circuit γ is opened by A2. 14 is opened, and the contents of the memory element 10 in the second memory circuit 7 are read out onto the data bus 3, as shown in FIG. 3(d).

At the same time, the internal address is subtracted by the internal address generation circuit 16, and the reading is completed.

Note that in the above embodiment, the internal address via the read/write permission transfer gates 13 and 11 is used for the read/write transfer gate) 14.1.
2 was opened to perform a read or write operation, but as shown in FIG.
′! ! -8 is fine.

In this case, the read or TA transfer gates 14, 12 are opened by a read signal or a write signal.

〔Effect of the invention〕

As described above, according to the present invention, by providing the address generation circuit inside the memory, it is possible to speed up the stack operation, which is the post-write destination read operation.

[Brief explanation of the drawing]

Figures 1 to 3 show one embodiment of the present invention.
Figure 2 is a diagram of the internal configuration of the memory, Figure 2 is a connection diagram between the CPU and memory, Figure 3 is a timing chart showing read/write operations, Figure 4 is a diagram showing another example of the memory configuration, Figure 5 is a connection diagram showing a conventional example, and FIG. 6 is a timing chart showing its operation. 1...Storage device (memory), 3...Data bus, 4...Control signal line, 5...Storage circuit array, 6
~9... Memory circuit, 10... Memory element, 11...
・φ・Writing permission transfer gate, 12...
-Write transfer gate, 13...Read permission transfer gate, 14...Read transfer gate, 1511...Chip selection transfer gate, 17...Clock signal input terminal.

Claims (2)

[Claims] (1) A memory device comprising a semiconductor integrated circuit, characterized in that it is equipped with an internal address generation circuit that generates an address signal at the same time as a read or write operation is performed. (2) The storage device according to claim 1, wherein writing is always performed at an address one address ahead of the read address in accordance with an address signal generated by an internal address generation circuit.