JPH029401Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to an adder circuit in a microcomputer.

[Technical background of the invention and its problems]

_The addition process in a conventional microcomputer will be explained using _FIG .
The process performs bit addition with data _D2 in the register inside and writes it to address _a0 again. However, with this kind of processing, especially
Since the addition process is performed within the CPU 1 using the program in the ROM ₂ , there is a drawback that the processing speed cannot be improved.

[Purpose of invention]

This idea was made in view of the above circumstances, and the purpose is to provide an addition circuit for a microcomputer that can improve processing speed by performing addition processing while the CPU only performs reading and writing processing.

[Summary of the idea]

For example, as shown in Figure 2, this idea uses RAM
11, a data bus 21, a latch circuit 16, an adder 13 loop, a CPU 14, an adder 13, a buffer circuit 12, and a RAM 11 line.

[Example of idea]

Examples of this invention will be described below with reference to the drawings. In FIG. 2, 20 is an address bus, and 21 is a data bus. In this microcomputer, data writing to the RAM 11 is performed as follows. CPU
14 first applies a reset signal to the latch circuit 16 through the input/output circuit 17. Therefore, the output of the latch circuit 16 becomes all zero, and the output of the adder 1
3 is added to one input end of the 3. Then, the adder 13 inputs the data from the CPU 14 as is to the buffer circuit 12. next,
When a write pulse is obtained from the CPU 14, the contents of the buffer circuit 12 are written to the RAM 12.

Next, read processing will be explained. During read processing, data in RAM11 is transferred to CPU1.
The data is read into the CPU 14 through the buffer circuit 15 by the memory read pulse MR of No. 4.

Next, the addition process will be explained with reference to FIG. 2 and FIG. 3 showing a timing chart. In this case, it is assumed that data _D2 is added to data _D1 at address _ao of the RAM 11 shown in FIG. 4a and stored as shown in FIG. 4b. First, with diming t ₁
Address a _o is given to RAM 11 (Figure 3 a),
After the access period, data _D1 is output onto the data bus 21 (FIG. 3b). Data _D1 read from the RAM 11 is passed through the latch circuit 16 to the adder when a latch pulse (equal to the falling edge of the write pulse (FIG. 3c)) for the latch circuit 16 is obtained at timing _t3 . 13 (Fig. 3e). In adder 13, at the same time as data D ₁ is input,
Bit addition is performed with data D ₂ (FIG. 3b) output from the CPU 14, and the result becomes input to the buffer circuit 12 at timing _t4 after the addition period (FIG. 3d). At this time, the write pulse is at a low level (FIG. 3c), so the data in the buffer circuit 12 is transferred to the RAM 11.
will be written in. The RAM 11 is set to be in a write mode when the write pulse is at a low level, and to be in a read mode at all other times, that is, when it is at a high level. Note that the buffer circuit 12 is in a high impedance state while the write pulse is at a high level to avoid collision with data read from the RAM 11. Also, when performing such addition processing, the CPU 14
A reset signal to the latch circuit 16 is set to high level through the input/output circuit 17, so that no latch operation is performed. Therefore, as soon as the write pulse rises and becomes high level, the RAM 11 enters the read mode, and the rest is as follows.
Just specify the address.

Therefore, the CPU 14 uses the address a _o of the RAM 11
If you specify and generate a write pulse,
Addition processing between the data _D2 in the CPU and the read data _D1 is automatically performed during the write pulse period, and the data is written to the specified address _ao again.

Of course, when importing data D ₂ into the CPU,
The data is taken in in advance through the buffer circuit 15 using a read pulse. Therefore, constant data D ₂
Very fast processing speeds can be obtained when adding a bit to data at each address, or when cumulatively adding data at a fixed address several times. There is no need to perform an addition operation, and this program step can be omitted.

[Effect of idea]

As described above, this invention can provide an addition circuit for a microcomputer with improved addition processing speed.

[Brief explanation of drawings]

Fig. 1 is a system configuration diagram of a microcomputer, Fig. 2 is a configuration explanatory diagram showing an embodiment of this invention, Fig. 3 is a timing chart shown to explain the operation of the circuit of this invention, and Fig. 4. 2 is an explanatory diagram showing an example of the memory space of the RAM shown in FIG. 2. FIG. 11...RAM, 12, 15...Buffer circuit, 13...Adder, 14...CPU, 16...
Latch circuit, 17... input/output circuit.

Claims (1)

[Claims for Utility Model Registration] A latch circuit that latches and outputs data read from a random access memory in response to a write pulse from a central processing unit; and output data of this latch circuit and the central processing unit. A microcomputer comprising: an adder that adds bits of output data from the adder; and a buffer circuit to which the output of the adder is added and adds an output to the random access memory during the write pulse period. Adder circuit in.