JP2960110B2 - RISC processor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Outline Industrial application field Conventional technology (Fig. 5) Problems to be solved by the invention Means for solving the problem (Fig. 1) Action Embodiment (a) One Description of the embodiment (FIGS. 2 to 4) (b) Description of another embodiment [Summary] When a RISC processor that does not generate a data strobe signal writes data into a storage unit such as a register or a memory. Regarding a RISC processor system that guarantees writing, an RISC processor that executes one instruction in one machine cycle for the purpose of guaranteeing the address and data hold time of the RISC processor, a storage unit, the RISC processor and the storage unit The RISC processor generates a data request signal and a write signal when writing to the storage unit, and In a RISC processor that outputs an address and data to a storage / data bus and writes data to the storage unit, the data request signal is input and a signal of a period necessary for guaranteeing a data writing period to the storage unit. And an AND gate that generates a data strobe signal for the storage unit based on the output of the flip-flop and the data request signal.

[Industrial applications]

The present invention relates to a RISC processor system that guarantees writing when a RISC processor that does not generate a data strobe signal writes data into a storage unit such as a register or a memory.

RISC with the recent demand for high-speed information processing systems
(Reduced Instruction Set Computer) processor is provided.

The RISC processor is a conventional CISC (Complex Instructio
In contrast to a (n Set Computer) processor, the number of instruction sets is limited and one instruction is executed in one machine cycle to increase the data processing speed.

In such a RISC processor, the number of input / output control signals is limited because priority is given to speeding up. In particular, an external circuit for guaranteeing writing is required.

[Conventional technology]

 FIG. 5 is an explanatory diagram of the prior art.

When the RISC processor 1 writes to the storage unit 2 such as a register or a memory via the bus 3, a data request *
DREQ and a write signal were output, and data was loaded on the bus 3.

By the way, in the CISC processor, since a data strobe signal is generated, many data hold and address bold times are guaranteed.

Since the RISC processor 1 executes one machine cycle 1, after accessing an external register, another register or memory may be accessed in the next cycle, and a data strobe signal is generated because data requests are continuous. Some are not.

For example, Advanced Micro Devices' 29,000 RISC MPU
Does not have a data strobe signal.

For this reason, the RISC processor uses a data request as a data strobe signal.

[Problems to be solved by the invention]

However, if the data request is a data strobe signal, there is a problem that the data strobe signal does not satisfy the address and data hold time.

Accordingly, an object of the present invention is to provide a RISC processor system capable of guaranteeing the address and data hold time of a RISC processor.

[Means for solving the problem]

As shown in FIG. 1, the present invention provides a RISC processor 1 for executing one instruction in one machine cycle, a storage unit 2,
An address / data bus 3 for connecting the RISC processor 1 to the storage unit; the RISC processor 1 generates a data request signal and a write signal when writing to the storage unit 2; In the RISC processor 1 which outputs an address and data to the address / data bus 3 and writes data to the storage unit 2, it is necessary to input the data request signal and to guarantee a data writing period to the storage unit 2. The flip-flop 40 outputs a signal during a short period, and an AND gate 41 that generates a data strobe signal for the storage unit 2 based on the output of the flip-flop 40 and the data request signal.

[Action]

According to the present invention, since the data strobe signal is generated by ANDing the delayed data request signal and the data request signal, the data strobe signal can be generated when the data is determined.

Therefore, even in the RISC processor, the address and data hold time at the time of writing can be guaranteed, and the writing can be guaranteed.

 Moreover, it can be realized with a simple configuration.

〔Example〕

 (A) Description of one embodiment FIG. 2 is a configuration diagram of one embodiment of the present invention.

In the figure, the same components as those shown in FIG. 1 are denoted by the same symbols, 3a is an address bus, and 3b is a data bus.

4 is a memory control circuit, which is a data request signal *
A control signal generator 4a that generates a data strobe signal DSTRB, a data ready signal * DRDY, and a data request cut signal DREQCUT from DEEQG, and a TREQ gate that cuts a continuous data request signal * DREQ from the RISC MPU1 with the data request cut signal DREQCUT A circuit 4b, a data request signal DREQG from the DREQ gate circuit 4b, a data strobe signal DSTB, and a read / write signal READ / WRITE.
A read / write control circuit 4c for generating an out enable signal * OE, a write enable signal * WE, and a chip select signal * CS for the static memory (SRAM) 2 and a memory select signal by decoding the address of the address bus 3a
And a decoder 4d for generating MEMSEL.

FIG. 3 is a detailed circuit diagram of FIG. 2, showing the memory (SRAM) control circuit of FIG.

In the figure, the same components as those shown in FIG. 2 are denoted by the same symbols.

The DREQ gate circuit 4b inverts the data request signal * DREQ from the RISC processor 1 and a data request cut signal DREQCUT to be described later, performs an AND operation, and outputs the inverted output DREQG. It has an AND gate 46 for ANDing the data request signal DREQG and the memory select signal MEMSEL.

The control signal generation circuit 4a outputs the data request signal DREQG of the AND gate 46 by the system clock SYSCLK,
A flip-flop 40 that outputs data ready DRDY1 to DRDY3 delayed by two clocks, two clocks and three clocks, a data ready DRDY2, a read signal READ, and an inverted data request signal * DREQG are inverted, an AND is taken, and a data strobe is taken. And a write assurance circuit including an AND gate 41 for generating a signal DSTRB.

Further, the control signal generating circuit 4a includes an inverter 43 for inverting the data ready DRDY3, and an AND gate 44 for ANDing the output of the inverter 43 and the data ready DRDY2 and outputting the inverted result as a data ready signal * DRDY. An AND of the data ready generation circuit and data ready DRDY2 and DRDY3 is taken, and the data request cut signal DREQCUT
And a cut signal generation circuit composed of an AND gate 42 for generating

The read / write control circuit 4c outputs a data request signal
An inverter 47 for inverting DREQG to generate a chip select signal * CS; an AND gate 48 for ANDing the data request signal DREQG and the read signal READ and generating the inverted signal as an out enable signal * OE; An AND gate 49 outputs an AND of DREQG and the data strobe signal DSTRB, and outputs the inverted signal as a write enable signal * WE.

 FIG. 4 is a time chart of one embodiment of the present invention.

In the drawing, a continuous (burst) access mode of write access and read access will be described.

The RISC processor 1 asserts the data request signal * DREQ at low level to access the memory 2, outputs an address to the address bus 3a, outputs data to the data bus 3b, and sets the read signal READ to low level (write instruction). I do.

The data request signal * DREQ passes through the AND gate 45, and is ANDed with the memory select signal MEMSEL by the AND gate 46. After passing through the gate, the data request signal DREQ
G.

This signal is input to a flip-flop (FF) 40, delayed by one clock with the system clock SYSCLK, and becomes a data ready DRDY1.

The data ready DRDY1 is re-input to the flip-flop 40, delayed by one clock, and becomes the data ready DRDY2.

Further, the data ready DRDY3 is re-input to the flip-flop 40 and is delayed by one clock to become the data ready DRDY3.

That is, the flip-flop 40 outputs the data request signal
Data ready DRDY1 to DRDY3 are generated by delaying DREQG by one clock, two clocks, and three clocks.

The data ready DRDY2 delayed by two clocks is inverted and input to the AND gate 41.

The AND gate 41 outputs the inverted data request signal * DREQ
G and the inversion of the read signal READ are input.

Therefore, when DREQG is at the high level in response to the write instruction from the AND gate 41, the data strobe signal DSTRB is output when the data ready DRDY2 is inverted.

That is, the data strobe signal DSTRB rises when the data request signal * DREQG is asserted, and falls when the second clock rises.

This means that the falling edge of the data strobe signal DSTRB at the 1.5th clock in the 2.5 clock write access period in the drawing is the start point of the data fetch.

At this point, the write data indicated by the data DATA in FIG. 4 has been determined on the data bus 3b, and the write data is guaranteed for at least one clock.

On the other hand, as in the conventional case, the data strobe signal DS
Assuming that TRB is the data request signal DREQG, the rising timing of DSTRB is the 2.5th clock from the assertion of DREQG, and is the point where write data has started to disappear,
Data is not guaranteed.

Further, the inverted data ready DRDY3 and the data ready DRDY2 via the inverter 43 are ANDed by the AND gate 44, and the data ready * DRDY is returned to the RISC processor 1.

Further, the AND of the data ready DRDY2 and the data DRDY3 is taken by the AND gate 42, and the data request cut signal DR
Generates EQCUT and controls the AND gate 45 of the DREQ gate circuit 4b.

The meaning of this data request cut signal DREQCUT is RIS
In the case of the C processor 1, the data request signal * DREQ is asserted and left at the time of continuous access, and is not negated every access unlike the CISC processor.

For this reason, the out enable * OE and the write enable * WE cannot be generated for each access, and the memory cannot be accessed in the normal memory sequence.

In addition, a check sequence of a general-purpose ECC or a parity check circuit cannot be obtained.

Therefore, the data request signal *
DREQ is negated by a data request cut signal DREQCUT for each access, and converted into a data request signal * DREQG for each access.

Finally, the read / write control circuit 4c inverts the data request signal DREQG for each access by the inverter 47 to generate the chip select signal * CS, and generates the out enable signal * OE from the AND gate 48 at the time of reading. And
At the time of writing, the write enable signal * WE is generated from the AND GENTHO 49 by the data strobe signal DSTRB and the data request signal DREQG, and the SRAM 2 is accessed.

In this way, no data strobe signal is generated
Even if the RISC processor 1 makes a write access to the SRAM 2, a data strobe signal can be generated when the address and data are sufficiently determined, and the address and data hold time is guaranteed, so that writing can be guaranteed.

(B) Description of Other Embodiments In addition to the above-described embodiments, the present invention can be modified as follows.

Although the description has been made using the SRAM as the storage unit, the present invention may be applied to a register such as a DRAM, a flip-flop, or a latch circuit.

Also, although data ready DRDY2 is used, the data ready signal * DR created from data ready DRDY2 and DRDY3
The data strobe signal DSTRB may be generated using DY and the data request signal * DREQG.

Although the present invention has been described with reference to the embodiments, the present invention can be variously modified in accordance with the gist of the present invention, and these are not excluded from the present invention.

〔The invention's effect〕

As described above, according to the present invention, the data request signal is delayed by the flip-flop 40,
Generates a data strobe signal by ANDing with the data request signal, so that the address,
An appropriate data hold time can be taken, and writing can be guaranteed.

 Further, it can be realized by a simple circuit.

[Brief description of the drawings]

 1 is a principle diagram of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a detailed circuit diagram of an embodiment of the present invention, and FIG. 4 is a time chart of an embodiment of the present invention. FIG. 5 is an explanatory view of the prior art. In the figure, 1 ... RISC processor, 2 ... storage unit, 3 ... address / data bus, 40 ... flip-flop, 41 ... AND gate.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) G06F 12/00 G06F 9/30

Claims (1)

(57) [Claims] 1. A RISC that executes one instruction in one machine cycle
A processor, a storage unit, and an address / data bus connecting the RISC processor and the storage unit. When writing to the storage unit, the RISC processor transmits a data request signal and a write signal to the storage unit. In a RISC processor which generates, outputs an address and data to the address / data bus, and writes data to the storage unit, it is necessary to input the data request signal and to guarantee a data writing period to the storage unit. A RISC processor system comprising: a flip-flop that outputs a signal for a predetermined period; and an AND gate that generates a data strobe signal for the storage unit based on the output of the flip-flop and the data request signal.