JP2923330B2 - Memory access control circuit of RISC processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Overview Industrial application Field of the Invention Problems to be Solved by the Invention Means for Solving the Problems (FIG. 1) Action Embodiment (a) Description of One Embodiment ( (FIGS. 2 to 4) (b) Description of Another Embodiment Effect of the Invention [Summary of the Invention] The present invention relates to a memory access control circuit for a RISC processor to continuously access a memory. A memory access control circuit of a RISC processor that receives a request signal from a RISC processor and controls access to a memory for the purpose of negating every memory access, a request gate circuit that negates the request signal by a gate signal, The gate signal is delayed for each access cycle based on the delayed signal. And a memory access circuit for generating a memory access signal based on the negated request signal.

[Industrial applications]

The present invention relates to a memory access control circuit for a RISC processor to continuously access a memory.

RISC with the recent demand for high-speed information processing systems
(Reduced Instruction Set Computer) processor is provided.

The RISC processor uses the conventional CISC (CompIex Instructio
As compared with an n Set Computer) processor, the number of instruction sets is limited, and one instruction is executed in one machine cycle to increase the data processing speed.

Therefore, in the RISC processor, a necessary control signal is continuously asserted in the continuous access, and a memory access control technique for that is required.

[Conventional technology]

RISC processor is a combination of SRAM and DRAM, SRAM and DRAM
When accessing a memory such as a VRAM, a data request or an instruction request is generated.

Generally, in a CISC processor, a data request and an instruction request are negated every memory access.

However, the RISC processor executes one machine cycle and executes one instruction, and prefetches the instruction in four words. Therefore, the memory is often accessed continuously. In this case,
Some of the above-mentioned requests continue to be asserted during continuous access.

For example, Advanced Micro Devices' 29,000 RISC MPU
Then, during continuous access, the request continues to be asserted.

[Problems to be solved by the invention]

However, the prior art has the following problems.

Since requests are continuously asserted during continuous access, it is okay to read / write consecutive addresses with one address using the nibble function of the memory. However, RAS and CAS cannot be generated for each memory access, and If they differ, continuous access is not possible.

Since it is not negated every memory access, a general-purpose one cannot be used for a data error detection circuit for detecting a data error every memory access, a byte number counter for data transfer, and the like, and a special one must be manufactured.

Therefore, an object of the present invention is to provide a memory access control circuit of a RISC processor that can negate a request signal for each access in a continuous access of the RISC processor.

[Means for solving the problem]

 FIG. 1 is a diagram illustrating the principle of the present invention.

As shown in FIG. 1, the present invention provides a memory access control circuit of a RISC processor which receives a request signal from a RISC processor 1 and controls access to a memory 2.
A request gate circuit 4b for negating the request signal with a gate signal, a control signal generation circuit 4a for delaying the gated request signal, and generating the gate signal for each access cycle based on the delayed signal, And a memory access circuit 4c for generating a memory access signal based on the negated request signal.

[Action]

In the present invention, a gate signal is generated for each access cycle by a request signal, and the request signal is negated by the gate signal. Therefore, a request signal that is continuously asserted at the time of continuous access is negated for each memory access, and the memory access circuit 4c Can be entered.

Therefore, in the memory access circuit 4c, RAS and CAS can be generated by the same operation as single access even in continuous access, and continuous access to the memory can be performed even if the address is different.

The negated request signal allows the data error detection circuit and the transfer byte number counter to operate in the same manner as in the prior art, so that general-purpose ones can be used.

〔Example〕

 (A) Description of one embodiment FIG. 2 is a block diagram of one embodiment of the present invention.

In the figure, the same components as those shown in FIG. 1 are denoted by the same symbols, 3a is an address bus, and 3b is a data bus.

Reference numeral 4 denotes a memory access control circuit, which outputs a data request cut signal DREQ CU from a data request signal * DREQG.
T, a control signal generation circuit 4a for generating a data ready signal * DRDY, a request gate circuit 4b for cutting a data request signal * DREQ from the RISC processor 1 by a data request cut signal DREQ CUT,
An arbitration circuit 4d for arbitrating the refresh of the DRAM 2, a data request signal and a read signal of the RISC processor 1, and a row address strobe * RAS, a column address strobe * CAS, an out enable * O
E, a write enable * WE is generated to the DRAM2, a memory address circuit 4c for addressing, a decoder 4e for decoding an address on the address bus 3a to generate a memory select signal MEMSEL, and an address on the address bus 3a as a row address. And a multiplexer 4f that outputs the column address to the DRAM 2 separately.

FIG. 3 is a detailed circuit diagram of FIG. 2, and shows a main part of the memory access control circuit 4 of FIG.

In the figure, the same components as those shown in FIG. 2 are denoted by the same symbols.

The request gate circuit 4b inverts the data request signal * DREQ from the RIS processor 1 and a data request cut signal DREQ CUT to be described later, performs an AND operation, and outputs a negated data request signal * DREQG obtained by inverting the result. AND gate 40, data request signal * DREQG, and request permission signal * IDREQ to be described later.
And an AND gate 41 for inverting OK, taking an AND, and outputting a permitted data request signal.

The arbitration circuit 4d is constituted by an AND gate, and inverts the inverted refresh enable signal * REF OK, the memory select signal MEMSEL, and the inverted data request signal * DREQG, and outputs the result as the permitted data request signal IDREQ OK. I do.

That is, when the memory is selected and refresh is not performed, the permitted data request signal IDREQ OK is generated.

The memory access circuit 4c delays the permitted data request signal IDREQ OK by one clock, two clocks, and three clocks with the system clock SYSCLK.
1, Q2, Q3, a one-clock delay signal Ql of the flip-flop 46 and a refresh RAS.
An OR gate 47a that takes off the signal and generates a row address strobe * RAS, and an off gate 47b that takes an OR of the 2-clock delay signal Q2 of the flip-flop 46 and the refresh CAS signal and generates a column address strobe * CAS Having.

Further, the memory access circuit 4c ANDs the permitted data request signal IDREQ OK, the read signal READ, and the two-clock delay signal Q2 of the flip-flop 46, and generates an out enable signal * OE, and an AND gate 48a.
Authorized data request signal IDREQ OK and write signal WR
An AND gate 48b for ANDing the iTE (inverted read signal) and the 3-clock delay signal Q3 of the flip-flop 46 and generating a write enable signal * WE is included.

The control signal generation circuit 4a outputs the permitted data request signal
IDREQ OK and 2-clock delay signal Q2 of flip-flop 46
AND gate 42 for ANDing the output of AND gate 42 and the output of AND gate 42 for one clock by system clock SYS CLK,
Delayed signals DRDY1 to DRDY delayed by two clocks and three clocks
A flip-flop 43 for generating RDY3, an AND gate 44 for ANDing one clock and three clock delay signals DRDY1 and DRDY3 of the flip-flop 43 and generating a data request cut signal DREQ CUT, and a three clock delay signal for the flip-flop 43 It has an inverter 45a for inverting DRDY3, and an AND gate 45b for ANDing the output of the inverter 45a and the two-clock delay signal DRDY2 of the flip-flop 43 and generating an inverted output as data ready * DRDY.

FIG. 4 is a time chart of one embodiment of the present invention.
This shows a state of continuous access.

The RISC processor 1 asserts the data request signal * DREQ at a low level upon access.

At the same time, the memory address is output to the address bus 3a, and in the case of a write access, the read signal READ is set to a low level (write instruction), and the write data is output to the data bus 3b.

The data request signal * DREQ passes through the AND gate 40, becomes * DREQG, and is input to the AND gate (arbitration circuit) 4d.

In the AND gate 4d, the memory select signal MEMSEL is at a high level from the decoder 4e and the inverted refresh signal * RE
When FOK is high, the data request signal * DREQ
G is permitted and the permitted data request signal IDREQ OK is generated.

That is, when the inverted refresh signal * REF OK is at the low level, the access is prohibited because the DRAM 2 is being refreshed.

The permitted data request signal IDREQ OK is input to the flip-flop 46 and generates delay signals Q1, Q2, and Q3 delayed by one clock, two clocks, and three clocks.

The low signal strobe * RAS is generated from the OR gate 47a by the delay signal Ql, and the column address strobe * CAS is generated from the OR gate 47b by the delay signal Q2.

On the other hand, the permitted data request signal * IDREQ OK is ANDed with the data request signal * DREQG by the AND gate 41 and input to the control signal generation circuit 4a.

In the control signal generation circuit 4a, the output of the AND gate 41 and the two-clock delay signal Q2 of the flip-flop 46 are ANDed by the AND gate 42, and the output is input to the flip-flop 43, and one clock and two clocks are input. And generates delay signals DRDY1 to DRDY3 delayed by three clocks.

The data ready signal * DRDY is generated from the AND gate 45b by the delay signals DRDY2 and DRDY3, and is returned to the RISC processor 1 as a response to the access.

The data request cut signal DREQ CUT is generated from the AND gate 44 by the delay signals DRDY1 and DRDY3, during which the AND gate 40 of the gate circuit 4b is closed.

Therefore, the data request signal * which continues to be asserted
DREQ is negated by the cut signal DREQ CUT for each memory access.

As a result, * DREQG is negated every access, and strobes * RAS, * CAS and data ready * DRDY can be generated every access.

On the other hand, out enable * OE is issued from AND gate 48a at the timing of delay signal Q2 at the time of reading, and write enable * WE is issued from AND gate 48b at the timing of delay signal Q3 at the time of writing.

In this way, the request signal that is continuously asserted at the time of continuous access is negated for each memory access, and even if the access is continuous, the RA is performed in the same operation as a single access.
S and CAS can be generated, and the same circuit can be operated even during single access.

(B) Description of Other Embodiments In addition to the above-described embodiments, the present invention can be modified as follows.

Although the description has been given of the example of the data request signal, the same applies to the case of the instruction request signal.

Although the memory has been described as a DRAM, it may be an SRAM or the like.

Although the present invention has been described with reference to the embodiments, the present invention can be variously modified in accordance with the gist of the present invention, and these are not excluded from the present invention.

[Effects of the Invention] As described above, the present invention has the following effects.

Since the request signal at the time of continuous memory access of the RISC processor is negated for each memory access, the control signal necessary for memory access can be generated with the same operation as the single access even for continuous access, and the address is different. Also, continuous access to the memory becomes possible.

By the negated request signal, peripheral circuits such as a data error detection circuit and a transfer byte number counter can perform the same operation as the conventional one, and a general-purpose one can be used.

[Brief description of the drawings]

1 is a principle diagram of the present invention, FIG. 2 is a block diagram of one embodiment of the present invention, FIG. 3 is a detailed circuit diagram of one embodiment of the present invention, and FIG. 4 is a time chart of one embodiment of the present invention. It is. In the figure, 1 ... RISC processor, 2 ... memory, 4 ... memory access control circuit, 4a ... control signal generation circuit, 4b ...
… Request gate circuit, 4c …… Memory access circuit.

Claims (1)

(57) [Claims] A memory access control circuit of a RISC processor for receiving a request signal from a RISC processor (1) and controlling access to a memory (2), comprising: a request gate circuit (4b) for negating the request signal by a gate signal. A control signal generating circuit (4a) for delaying the gated request signal and generating the gate signal for each access cycle based on the delayed signal; and a memory access signal based on the negated request signal. A memory access control circuit for a RISC processor, comprising: a memory access circuit (4c) that generates the memory access circuit.