JPS6383851A - System for discriminating input/output data - Google Patents

Abstract

PURPOSE:To omit the external circuits and to increase the data access speed by using plural input pins for data complete signals and producing an OR within a microprocessor. CONSTITUTION:The inverse of DC0 input signal is supplied to test machine 21 via an inverter 28, a NOR gate 29 and an inverter 30, while the inverse of DC1 input signal is supplied to the machine 21 via an inverter 32, the gate 29 and the inverter 30 respectively. For the input signal of a microprocessor, plural inverters are generally cascaded at the stages following an input pad. These inverters are replaced with NOR and an OR is secured. The circuit delay due to the cascade of inverters and the circuit delay caused when the circuit delay serves as a NOR by an amount equal to a stage are very small in a CMOS process. Thus it is not required to produce an OR through an external circuit, therefore, the data access speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data input/output method for a microprocessor, and particularly to connection of an external cache.

[Conventional technology]

Conventionally, when a microprocessor performs data input/output, most microprocessors use a method in which the memory system or input/output device returns a signal to the microprocessor indicating that data reading/writing has been completed. has been done. For example, IE Micro, Volume 5, No. 6 (December 1985)
Monthly, pages 4 to 22 (IEEE, Micro,
Vo45. A.S.

p4-p22. DEC, 1985), the Intel 80386 uses l'(,
By setting the EADY signal to low level, input/output data is acknowledged.

In the above-mentioned 80386, there is only one input signal pin, eady-, for acknowledging input/output data.

Other microprocessors also have only one input signal for input/output data, and no microprocessor has multiple input signals.

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In the above conventional technology, when a cache or a numerical coprocessor is connected in addition to the memory system, the data output signals generated by each are ORed by an external circuit, and the data coprocessor of the microprocessor is
It was necessary to input it to the bleat signal. For this reason, there is a problem in that a delay occurs due to the external circuit, and data access becomes slow.

An object of the present invention is to eliminate external circuits and speed up data access.

[Means for solving problems]

The above object is achieved by providing a plurality of data complete signals as input signals to the microprocessor and generating a logical sum within the microprocessor.

[Effect]

A microprocessor that receives multiple data completes generates a logical OR within the chip, but the microprocessor's input signal is normally processed by multiple inverters connected in series after the input pad. A logical OR is constructed by rewriting . In the CMOS process, the circuit delay due to the cascade connection of inverters and the circuit delay when -stages of the inverters are NAND or N0RK are extremely small. This eliminates the need to generate a logical OR using an external circuit, and speeds up data access.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram illustrating a microprocessor system according to the present invention. The microprocessor 1 outputs an address line, a master type 3-0 (AT3-0) signal, a read/write (R/W) signal, and an address strobe (As signal) to the memory system 2 and coprocessor 3 to read/write data. Make a write request.

Address lines, R, /W double signals AS are signals that conventional microprocessors also have. The AT3-O signal is
This is a signal indicating the type of external access. For example, in the conventional microprocessor Intel Corporation 80386, the data/control CD/C) signal and the memo IJ/IOCM
/IO) signal is a signal indicating the type of external access, and Motorola's function code (Fe2-
1) (l is a signal indicating the type of external access.

Table 1 shows an example of AT3-00 allocation in the present invention.

The memory system is selected when AT2=O.

Also, AT3=1. A coprocessor is selected when AT2=1. AT3. AT2. ATL, ATO=0. 1
．． When it is 00, it indicates the interrupt accrual cycle kf, AT
3. AT2. ATL, ATO=0°1, 0. Select the control register space of Tokiko processor 1 and specify all register numbers using the address line.

The assignment of Table IAT3-0 is similar to that of whistle 1, and when data input/output is completed in memory system 2, DCO'e is asserted (when a low level is detected, the current cycle is ended).

The fun processor 3 is AT3. 2. 1. 0=01
If 01 specifies access to internal registers, and AT3,2=1.1 specifies commands, instruction addresses, and data transfer between the microprocessor and coprocessor, I)-microprocessor 1 of the specified data is D.C.
When '5r is detected in the low level of I, the current bus cycle is ended.

FIG. 2 shows the system of FIG. 1. FIG. 3 is a diagram showing a timing chart of data access.

FIG. 3 shows a flowchart when the microprocessor reads data, and FIG. 4 shows a flowchart when the microprocessor writes data.

In FIG. 2, CLK represents the operating clock of the microprocessor, memory system, and coprocessor.

At clock 1, the microprocessor outputs the address AT3-0 and outputs the address AT3-0 and outputs the address AT3-0 and outputs the address AT3-0 at the address level A of n/Wt.
Se asserts (low level coherence).

As is negated (]・level) at clock 3.

The memory system outputs the data at the address indicated by the address to the data bus, and asserts DCO at clock 4. The microprocessor detects a low level on DCO at clock 4, ends the current bus cycle, and proceeds to the next bus cycle.

Clock 5 to clock 8 indicate the timing of writing to the coprocessor. The microprocessor outputs write data onto the data bus.

Other than this, it is the same as the memory access from clock 1 to clock 4.

Clock 9 to clock 14 indicate memory access with wait cycles. Memory system clock 1~4
Memory access is delayed by one clock cycle compared to . For coprocessor access, D
The wait cycle is continued until the CI aborts δn, extending the current bus cycle.

FIG. 5 is an example of the configuration of a circuit within a microprocessor that implements the timing chart of FIG. 2. When the state machine 21 receives an input/output request signal 22 from a microprogram (not shown) inside the microprocessor, it starts data input/output operations. At this time, the address output register (AOR) 23. The access type output register (ATE) 24 and data output register (DOR) 25 are set by the microprogram.
Output data has already been set. Also, state machine/1
is PLA (7'loglample logic array Hpro
This can be realized using a grammable Logic Array or the like. These circuits were also used in conventional microprocessors.

-) 29. It is input to the state machine 21 through the inverter 30%. Similarly, DC1 input signal NOR gate 29, inverter 30 all pass through state machine 21
is input to. Normally, two to three stages of input inverters are connected after the bonding bat 27 of the DCO. Change one stage of these to a NOR gate, DCO, DC
I am taking the logical interest rate.

Here, by changing the threshold value 'd pressure of the inverter 28, 32 through a process, the DCO input can be made TTL level compatible and the DCl can be made MO8 level compatible.

FIG. 6 is a diagram showing another embodiment of the present invention.

In FIG. 6, the DCO input signal is input to the state machine 21 through an inverter 28, a NOR gate 29, and an inverter 3Qe, as in FIG. Data input/output is controlled based on the request signal 22.

On the other hand, the DC1 input signal is input to the gate 29 through the input gate 32 and the synchronization circuit 45'.
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It consists of 35. Latches 33 and 35 latch input data when CLK is at a high level, and latch 34 latches input data when CLK is at a low level. The latch 33 is
Clocked inverter 36°38 and inverter 37
It consists of

Similarly, the launches 34, 35 are connected to clocked inverters 39, 41 and 42, 44, and inverter 40, respectively.
and 43. Clocked inverters 36, 41, and 42 are conductive when CLK is at a high level, and clocked inverters 38, 41, and 44 are conductive when CLK is at a low level.

According to the configuration of FIG. 6, the DCO is used as a data complete input signal for synchronization, and the DCI is asynchronous. FIG. 7 is another embodiment of the present invention. , the input signals are sent to the inverter 28, the NOR gate 29 . Inverter 3
0 to statemachine/21. As in FIGS. 5 and 6, the state machine 21 receives an input/output request signal 22.
controls input/output operations.

On the other hand, the DC1 input signal passes through the level conversion circuit 50 to
The signal is input to the inverter 32. for example.

As a level conversion circuit, ECL (emitter couple logic) is used.
A conversion circuit from c) to 0MO8 can be considered. In this case, the DCO input signal can be used as a TTL or (MO8 level input pin), and the DC1 human power signal can be used as an input pin from ECL logic.

〔Effect of the invention〕

According to the present invention, an OR circuit for an output signal when inputting and outputting data is provided in a microprocessor chip. For this reason, an external NOR gate, e.g. 74A
The circuit delay of SO2 (delay time ~4.5 ns) is eliminated, making it possible to speed up memory access.

[Brief explanation of the drawing]

FIG. 1 is an example of a system configuration to which the present invention is applied, and FIG. 2 is a timing chart of one embodiment of the present invention. 3 and 4 are flowcharts for read/write, respectively, FIG. 5 is an example of an internal configuration of a microprocessor that realizes the timing chart of FIG. 2, and FIGS. 6 and 7 are respectively another embodiment of the present invention. Deman / M / 747g7' company,,j lO A L'am person lL
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Claims (1)

[Claims] 1. The microprocessor outputs an address signal, an address strobe signal, and a read/write signal to request memory access, and the memory system outputs the address signal,
In an input/output data access method in which an address strobe signal and a read/write signal are input and a data complete signal indicating completion of data reading/data writing is returned to the microprocessor, the microprocessor inputs multiple data complete signals. An input/output data identification method characterized by having an input pin.