JP2668215B2 - Micro computer - Google Patents

Description

The present invention relates to a microcomputer having a data bus and an address bus for accessing an external peripheral circuit. [Prior Art] In a conventional microcomputer, for example, a Rockwell R6500 microcomputer system is used.
As described in Chapter 1 of the Hardware Manual, the system clock is φ1 and φ2 is 180 ° out of phase with φ1.
It has two system clocks and is a basic timing signal for each component of the microcomputer. The operation is shown in the time chart of FIG. 1
Is an address delay time, 2 is a data setup time in a read cycle, 3 is an address access time of a peripheral circuit, and 4 is a bus cycle. The operation is as follows: the microcomputer outputs an address to the external address bus via the internal address bus at the system clock φ1, and the system clock φ2 outputs the data on the external data bus via the internal data bus. Input to the internal register. Usually, in this system, the address output circuit has a half-latch structure in order to guarantee the AC characteristics. Therefore, during the period of φ1 = “H”, the address becomes
Will be determined. Further, the data input circuit has a data through configuration and passes data on the external data bus at the timing of φ2 = “H” and inputs the data to the internal register via the internal data bus. [Problems to be Solved by the Invention] However, since the conventional microcomputer has the above-mentioned configuration, the delay time 1 of the address occupied in one bus cycle is large due to the AC characteristics, and The setup time 2 for inputting data was also a large proportion. Therefore, the address access time of the external peripheral circuit is 3
On the other hand, the bus cycle 4 is very long, which causes a problem that the execution speed of the microcomputer is reduced. An object of the present invention is to solve such a problem and shorten the bus cycle 4 of the microprocessor to increase the execution speed. [Means for Solving the Problems] The microcomputer of the present invention includes a control clock generating means for generating a plurality of control clocks having different phases from a basic clock, and an input data holding means for holding data input from the outside. Output of an address from a register to an internal address bus and output of the address from the internal address bus to an external address bus are controlled by timing signals formed based on the control clocks different from each other, and the input data holding means The timing for holding the data and the timing for outputting the data to the internal data bus are controlled by timing signals formed based on the different control clocks. A microcomputer according to the present invention is a microcomputer having an external data bus for accessing an external peripheral circuit, comprising: an internal data bus; a system clock generating circuit for generating three system clocks having phases different from each other; An input circuit, wherein a timing of holding data from the external data bus in the data input circuit and a timing of outputting data of the data input circuit to the internal data bus are controlled by different system clocks. It is characterized by. [Operation] According to the above configuration of the present invention, the address delay time,
Since the data setup time can be minimized, a microcomputer operating with a high-speed bus cycle can be realized. Embodiment FIG. 1 is a block diagram showing one embodiment of the present invention, in which 5 is an external data bus, 6 is a data input circuit having a half-latch configuration, 7 is a data output circuit, 8 is an internal data bus, 9 ACC, X, Y, S, PCH, PCL, P, A, B, C are internal registers, 10 is an arithmetic and logic unit (ALU), 11 is an internal address bus, 12 is a flip-flop address output Circuit, 13 is an external address bus, 14, 15, and 16 are system clocks S1, S2, S3, and 17 are the three system clocks S1, S, respectively.
2, a system clock generating circuit that generates S3, 18 is a control circuit, 19 is a timing signal that the data input circuit 6 latches data on the external data bus 5, and 20 is a timing signal that the data input circuit 6 latches. Timing signals for outputting the data stored in the internal data bus 8 to the internal data bus 8; timing signals 21 and 22 for outputting the data of the internal register 9 to the internal address bus 11; Is a timing signal for taking in the data of FIG. FIG. 3 is a time chart showing the operation of this embodiment. 1 to 4 and 19 to 23 are common to FIG. 2 and FIG. 1, respectively. S1, S2, and S3 are system clocks having phases different from each other by 120 ° in terms of logical design. In S1, mainly data from the data input circuit 6 is transferred to the internal register 9 via the internal data bus 8.
S2 is a waiting time until the control circuit 18 outputs the control signals 19 to 23, and is a timing at which various temporary registers of the microcomputer latch data. S3 is a timing for mainly performing data transfer between the internal registers 9, outputting an address to the external address bus 13 via the internal address bus 11, or latching input data to the data input circuit 6. In the microcomputer of this embodiment, the timing signal 2 is previously set at the falling edge of the timing signal 23.
At the timing of 1,22, the address output on the internal address bus 11 is output to the external address bus 13. Since the address output circuit 12 has a flip-flop configuration, the address delay time 1 with respect to the fall of the timing signal 23 is set.
Is only the delay time of the short path from the flip-flop to the output driver, which is the shortest in the circuit configuration. As for the data input, the data on the external data bus 5 is latched by the data input circuit 6 at the falling edge of the timing signal 19, and the latched data at the next timing of the timing signal 20 is converted into the internal data. Transfer to the internal register 9 via the bus 8. Therefore, the data setup time 2 for the fall of the timing signal 19 is
The delay time from the external data bus 5 to the data input circuit 6 is also kept to the shortest time in the circuit configuration. [Effects of the Invention] A microcomputer of the present invention includes a control clock generating means for generating a plurality of control clocks having different phases from a basic clock, and an input data holding means for holding data input from the outside, and The output of the address to the internal address bus and the output of the address from the internal address bus to the external address bus are controlled by a timing signal formed based on the different control clocks, and the data of the input data holding means is Since the timing of holding and the timing of outputting the data to the internal data bus are controlled by timing signals formed based on the different control clocks, the microcomputer occupies the bus cycle on the AC characteristics. Time, ie address Delay time, or it is possible to shorten the data setup time. That is, according to the microcomputer of the present invention, it is possible to provide a system with higher processing capability for peripheral circuits having a fixed address access time.

[Brief description of the drawings] FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a time chart showing the operation of the conventional technique. FIG. 3 is a time chart showing the operation of FIG. In the figure, 5 is an external data bus 13 is the external address bus 14, 15 and 16 are system clocks S1, S2 and S3, respectively. 1 is the delay time of the address 2 is the data setup time 3 is the address access time of the peripheral circuit 4 indicates a bus cycle

Continuation of front page    (56) References JP-A-60-83166 (JP, A)                 JP-A-60-215236 (JP, A)                 JP 62-182824 (JP, A)

Claims (1)

(57) [Claims] Control clock generating means for generating a plurality of control clocks having different phases from the basic clock; and input data holding means for holding data input from the outside; outputting an address from a register to an internal address bus; The output of the address from the bus to the external address bus is controlled by a timing signal formed based on the control clocks different from each other, and the timing of holding the data of the input data holding means and outputting the data to the internal data bus A microcomputer which is controlled by a timing signal formed based on the control clocks different from each other. 2. A microcomputer having an external data bus for accessing an external peripheral circuit, comprising: an internal data bus; a system clock generating circuit for generating three system clocks having mutually different phases; and a data input circuit; A microcomputer characterized in that timing for holding data from a bus in the data input circuit and timing for outputting data from the data input circuit to the internal data bus are controlled by the different system clock. 3. An address output from the register to the internal address bus, having an external address bus and an internal address bus;
3. The microcomputer according to claim 2, wherein control from said internal address bus to said external address bus is performed by said different system clock.