JP4008196B2 - Register control device and multi-CPU system - Google Patents

Description

上記以外の条件 ならば、（出力データ：スレーブラッチ１９の保持データ）
選択信号生成回路１７ｂは、データ選択部１７ａに例えば上記２つの条件に対応する選択信号（例えば、前者が成立している場合はハイレベル，後者が成立している場合はロウレベル）を出力し、データ選択部１７ａはその選択信号に応じて２つの入力端子の内の一方を選択するようになっている。
【００２５】
マスタラッチ１８のラッチ信号は、３入力のＡＮＤゲート２１によって与えられるようになっている。ＡＮＤゲート２１の入力端子には、ＣＰＵ１１または１２がライトサイクルの実行時にアクティブ（ハイ）にするライト信号と、二相クロック信号のＢ相信号ＣＫＢと、ＯＲゲート２２の出力信号とが与えられている。３入力のＯＲゲート２２には、アドレスデコーダ１３が出力する３つのデコード信号TIER，TIER0W，TIER1Wが夫々与えられている。
【００２６】
また、スレーブラッチ１９のラッチ信号には、二相クロック信号のＡ相信号ＣＫＡが直接与えられており、出力バッファ２０には、ＡＮＤゲート２３の出力信号がイネーブル信号として与えられている。ＡＮＤゲート２３の入力端子には、アドレスデコーダ１３が出力するデコード信号TIERと、ＣＰＵ１１または１２のリード信号とが与えられている。
【００２７】
尚、TIERレジスタ１４は、レジスタ部（レジスタ）１４ａとレジスタ制御部１４ｂとに分類される。レジスタ部１４ａは、マスタラッチ１８，スレーブラッチ１９，出力バッファ２０，及びＡＮＤゲート２１及び２３からなる部分であり、レジスタ制御部１４ｂは、マルチプレクサ１７，ＡＮＤゲート２１及びＯＲゲート２２からなる部分である。
【００２８】
そして、レジスタ制御部１４ｂに、アドレスデコーダ１３，TIER0Wレジスタ１５及びTIER1Wレジスタ１６を加えたものが、レジスタ制御装置２４を構成している。更に、レジスタ部１４ａとレジスタ制御装置２４にＣＰＵ１１及び１２を加えたものが、マルチＣＰＵシステム２５を構成している。
【００２９】
次に、本実施例の作用について図２をも参照して説明する。
▲１▼＜ビット操作命令によってTIERレジスタ１４に“１”をセットする場合＞
例えば、ＣＰＵ１１が、TIERレジスタ１４の第０ビットを“１”にセットするためのビット操作を実行するためＲＭＷサイクルを行う場合には、TIERレジスタ１４に対してではなく、TIER1Wレジスタ１６に対してＲＭＷサイクルを行うようにする。すると、時刻Ｔ１においてTIER1Wレジスタ１６よりデータ００ｈが読み出される。ＣＰＵ１１は、読み出したデータの第０ビットのみを“１”にセットするように内部レジスタの操作を行うと、時刻Ｔ３において同じTIER1Wレジスタ１６のアドレスを出力してデータ０１ｈのライトサイクルを行う。
【００３０】
この場合、読出し専用レジスタであるTIER1Wレジスタ１６への書き込みは行われず、それに代えて、デコード信号TIER1Wが出力されてＯＲゲート２２の出力端子がハイレベルになることから、クロック信号ＣＫＢの立上がりタイミングでＡＮＤゲート２１の出力端子もハイレベルとなって、TIERレジスタ１４のマスタラッチ１８にデータが書き込まれる。
【００３１】
また、各ビットセル１４Ｂ（０）〜１４Ｂ（７）においては、デコード信号TIER1Wが出力されているので、データバス４上にデータ値“１”が出力されているビットセル１４Ｂ（０）のデータ選択部１７ａは、選択信号生成回路１７ｂが出力する選択信号（ハイレベル）に応じてマスタラッチ１８にデータバス４（Ｄ（０））のデータ値“１”を選択して出力する。
【００３２】
それ以外のビットセル１４Ｂ（１）〜１４Ｂ（７）においては、選択信号生成回路１７ｂが選択信号をロウレベルにするので、データ選択部１７ａはマスタラッチ１８にスレーブラッチ１９の保持データを選択して出力する。この時点におけるスレーブラッチ１９の保持データは、時刻Ｔ３におけるライトサイクルによって書き換えられる前のデータ００ｈである。
【００３３】
即ち、ＣＰＵ１１のビット操作命令によって“１”がセットされるビット以外のビットデータは、ＣＰＵ１１がデータバス４上に出力しているデータにかかわらずスレーブラッチ１９の保持データが選択されて書き込まれることになる。結果として、マスタラッチ１８には、データ００ｈの第０ビットだけが“１”にセットされたデータ０１ｈが書き込まれる。そして、スレーブラッチ１９のデータは、時刻Ｔ３後のクロック信号ＣＫＡの立上がりタイミングで、マスタラッチ１８に書きまれているデータと同じデータ０１ｈに更新される。
【００３４】
従って、図５に示した従来例と同様に、もう１つのＣＰＵ１２が時刻Ｔ２においてＲＭＷサイクルを開始したとすると、ＣＰＵ１２は、時刻Ｔ２においてTIER1Wレジスタ１６のデータ値“００ｈ”を読み出してビット操作（第４ビットを“１”にセット）を行い、その操作結果のデータ値“１０ｈ”を時刻Ｔ４においてTIER1Wレジスタ１６のアドレスに書き込む。
【００３５】
すると、上記と同様のプロセスによって、データバス４上にデータ値“１”が出力されているビットセル１４Ｂ（４）のデータ選択部１７ａは、マスタラッチ１８にデータ値“１”を選択して出力し、それ以外のビットセル１４Ｂ（０）〜１４Ｂ（３），１４Ｂ（５）〜１４Ｂ（７）のデータ選択部１７ａは、マスタラッチ１８にスレーブラッチ１９の保持データを選択して出力する。
【００３６】
即ち、ＣＰＵ１２が時刻Ｔ４においてＲＭＷサイクル後半のライトサイクルを行う時点では、ＣＰＵ１１によるＲＭＷサイクルが完了している。従って、スレーブラッチ１９の保持データは０１ｈに更新されているので、TIERレジスタ１４のマスタラッチ１８（８ビット分）には、０１ｈデータの第４ビットを“１”に変更したデータ１１ｈが書き込まれることになる。
【００３７】
▲２▼＜ビット操作命令によってTIERレジスタ１４に“０”をセットする場合＞
また、例えば、TIERレジスタ１４の初期値が７７ｈである場合に、ＣＰＵ１１が、TIERレジスタ１４の第０ビットを“０”にセットするためのビット操作を実行するためＲＭＷサイクルを行う場合には、TIER0Wレジスタ１５に対してＲＭＷサイクルを行うようにする。すると、時刻Ｔ１においてTIER0Wレジスタ１５よりデータＦＦｈが読み出される。ＣＰＵ１１は、時刻Ｔ２でその第０ビットのみを“０”にセットすると、時刻Ｔ３において同じTIER1Wレジスタ１６のアドレスを出力してデータＦＥｈのライトサイクルを行う。
【００３８】
この場合、デコード信号TIER0Wが出力されてＯＲゲート２２の出力端子がハイレベルになることから、クロック信号ＣＫＢの立上がりタイミングでＡＮＤゲート２１の出力端子もハイレベルとなって、TIERレジスタ１４のマスタラッチ１８にデータが書き込まれる。
【００３９】
また、各ビットセル１４Ｂ（０）〜１４Ｂ（７）においては、デコード信号TIER0Wが出力されているので、データバス４上にデータ値“０”が出力されているビットセル１４Ｂ（０）のデータ選択部１７ａは、マスタラッチ１８にデータバス４（Ｄ（０））のデータ値“０”を選択して出力し、それ以外のビットセル１４Ｂ（１）〜１４Ｂ（７）のデータ選択部１７ａは、マスタラッチ１８にスレーブラッチ１９の保持データを選択して出力する。
【００４０】
従って、この場合も、ＣＰＵ１１のビット操作命令によって“０”がセットされるビット以外のビットデータは、ＣＰＵ１１がデータバス４上に出力しているデータにかかわらずスレーブラッチ１９の保持データが選択されて書き込まれることになる。スレーブラッチ１９の保持データは７７ｈであるから、その第０ビットが“０”にセットされることによってTIERレジスタ１４のマスタラッチ１８に書き込まれるデータは７６ｈとなる。
尚、上記のプロセスを、ＣＰＵ１１と１２とのアクセス順序を入れ替えて行ったとしても、全く同様の結果になることは言うまでもない。
【００４１】
▲３▼＜リードサイクルによってTIERレジスタ１４からデータを読み出す場合＞
例えば、ＣＰＵ１１が、TIERレジスタ１４のデータを単に読出す場合には、通常通りTIERレジスタ１４に対してリードサイクルを行うようにする。すると、アドレスデコーダ１３がデコード信号TIERを出力するのでＡＮＤゲート２３の出力端子がハイレベルとなる。そして、出力バッファ２０がイネーブルとなるので、スレーブラッチ１９に保持されているデータがデータバス４上に出力される。
【００４２】
▲４▼＜ライトサイクルによってTIERレジスタ１４に任意のデータを書込む場合＞
例えば、ＣＰＵ１１が、TIERレジスタ１４にデータ００ｈを書き込む場合には、通常通りTIERレジスタ１４に対してライトサイクルを行うようにする。この場合も、アドレスデコーダ１３がデコード信号TIERを出力するので、全てのビットセル１４Ｂの選択信号生成回路１７ｂがハイレベルの選択信号を出力する。従って、データ選択部１７ａは、ＣＰＵ１１が出力したデータバス４上のデータを選択してマスタラッチ１８に出力する。
【００４３】
そして、ＯＲゲート２２の出力端子がハイレベルになり、クロック信号ＣＫＢの立上がりタイミングでＡＮＤゲート２１の出力端子もハイレベルとなるので、TIERレジスタ１４のマスタラッチ１８にデータ００ｈが書き込まれる。
【００４４】
以上のように本実施例によれば、ＣＰＵ１１がビット操作命令を実行し、TIERレジスタ１４の任意のビットのデータ値を“１”にセットする場合は、ＲＭＷサイクル前半のリードサイクルにおいてTIER1Wレジスタ１６をアクセスしてデータを読み出し、変更対象ビットのデータ値を“１”にしてからTIER1Wレジスタ１６のアドレスでライトサイクルを行うと、マルチプレクサ１７は、TIERレジスタ１４のマスタラッチ１８に対して、データ値が“１”に変更されたビットについてはそのデータ値“１”を出力し、それ以外のビットについてはスレーブラッチ１９の保持データを出力するように選択する。
【００４５】
また、ＣＰＵ１１がTIERレジスタ１４の任意のビットのデータ値を“０”にセットする場合は、ＲＭＷサイクル前半のリードサイクルにおいて、TIER0Wレジスタ１５をアクセスしてデータを読み出し、変更対象ビットのデータ値を“０”にしてからTIER0Wレジスタ１５のアドレスでライトサイクルを行うと、マルチプレクサ１７は、マスタラッチ１８に対してデータ値が“０”に変更されたビットについてはそのデータ値“０”を出力し、それ以外のビットについてはスレーブラッチ１９の保持データを出力するように選択するようにした。
【００４６】
即ち、ＣＰＵ１１が行ったＲＭＷサイクルが完了する前に他のＣＰＵ１２がＲＭＷサイクルを開始したとしても、ＣＰＵ１２による後半のライトサイクルが行われる時点ではＣＰＵ１１によるＲＭＷサイクルは完了しているので、その変更後のデータがスレーブラッチ１９に保持されている。従って、ＣＰＵ１２によるライトサイクルでマスタラッチ１９に書き込まれるデータは、ＣＰＵ１２が変更しなかったビットについてはＣＰＵ１１によって変更されたデータとなるので、複数のＣＰＵによってアクセスされるTIERレジスタ１４のデータ値が、常に期待値通りとなるように制御することができる。
【００４７】
また、本実施例によれば、選択信号生成回路１７ｂにおいて、データ選択部１７ａが出力データにデータＤ（ｉ）を選択する条件に、“又は（デコード信号がレジスタ）”をも加えたので、ＣＰＵ１１または１２は、TIERレジスタ１４に対してビット操作により設定を行うだけでなく、TIERレジスタ１４に割り当てられているアドレスを出力して通常の任意データの書き込み（全ビットの同時書き込み）を行うこともできる。
【００４８】
そして、レジスタ制御装置２４を備えたことで、予めマルチＣＰＵシステムに適用することを想定した設計が行われていないＣＰＵ１１，１２を用いても、TIERレジスタ１４等の周辺回路を共用するマルチＣＰＵシステム２５を構成することが可能となる。
【００４９】
本発明は上記し且つ図面に記載した実施例にのみ限定されるものではなく、次のような変形または拡張が可能である。
単一ビットのビット操作に限ることなく、複数ビットのビット操作（所謂ビットフィールド操作）を行う場合でも、同様に適用することができる。
データバスサイズは８ビットに限ることなく，４ビット，１６ビットや３２ビットでも良い。
レジスタはコントロールレジスタに限らず、データレジスタでも良い。また、ダブルラッチ構成のTIERレジスタ１４に限ることなく、ＣＰＵの動作クロックに同期して動作するＤフリップフロップなどを用いてレジスタを構成しても良い。
リード信号とライト信号とを、例えばハイレベルの場合にリードサイクル，ロウレベルの場合にライトサイクルであることを示す１つの信号（リード／ライト信号）にしても良い。この場合、ＡＮＤゲート２１の対応する入力端子には、インバータゲートを介してリード／ライト信号を与えたり、或いは、当該入力端子は負論理とすれば良い。
【００５０】
ＣＰＵが３つ以上存在するシステムに適用しても良い。
マルチＣＰＵシステム全体を、半導体基板上の集積回路装置として構成しても良いし、各個別のディスクリート素子をプリント基板に搭載した回路装置として構成しても良い。
【図面の簡単な説明】
【図１】本発明の一実施例であり、TIERレジスタを中心とする電気的構成を示す図
【図２】２つのＣＰＵがリード・モディファイ・ライトサイクルを行う場合における、TIERレジスタのデータ値の変化を示すタイミングチャート
【図３】従来技術を示す図１相当図
【図４】二相クロック信号の波形を示す図
【図５】図２相当図
【符号の説明】
１１，１２はＣＰＵ、１３はアドレスデコーダ、１４はTIERレジスタ、１４ａはレジスタ部（レジスタ）、１４ｂはレジスタ制御部、１５はTIER0Wレジスタ（“０”セット用レジスタ）、１６はTIER1Wレジスタ（“１”セット用レジスタ）、１７はマルチプレクサ、１８はマスタラッチ、１９はスレーブラッチ、２４はレジスタ制御装置、２５はマルチＣＰＵシステムを示す。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a register control device for controlling data values of registers accessed by a plurality of CPUs, and a multi-CPU system including the register control device.
[0002]
[Prior art]
In a multi-CPU system configured to implement advanced functions with multiple CPUs, when each CPU attempts to execute a read cycle or a write cycle, only one CPU always uses the bus exclusively Thus, the right to use the bus is arbitrated by the arbiter.
[0003]
In such a system, when the peripheral circuit such as the control register is shared, or when setting is performed after checking the value of the semaphore, the CPU performs a bit operation on (read) data read from a certain register. (Modify), a read-modify-write cycle in which the data value resulting from the bit manipulation is written back to the same register (write) may be executed.
[0004]
Depending on the type of CPU, there is a type in which each signal is output so that the read / modify / write cycle is inseparably executed and the bus is continuously occupied. However, assuming that a multi-CPU system is configured using a CPU that does not have such a function, the following problems may occur.
[0005]
[Problems to be solved by the invention]
FIG. 3 is a configuration example of the multi-CPU system. The CPUs 1 and 2 are connected to the address bus 3 and the data bus 4, and both can access the register 5. The size of the data bus 4 is assumed to be 8 bits, for example. Register 5, for example, is a control register (TIER: Timer Interrupt Enable Register) for setting whether or not each timer interrupt is possible with an 8-channel timer. Bits 0 to 3 are set by CPU 1 and 4 to 7 are set by the CPU 2.
[0006]
The address decoder 6 connected to the address bus 3 decodes the address output by the CPU 1 or 2 and outputs, for example, a decode signal TIER to the TIER register 5 when the TIER register 5 is accessed. It has become. When the CPU 1 or 2 executes a bus cycle, the right to use the buses 3 and 4 is arbitrated by an arbiter (not shown) as described above.
[0007]
The TIER register 5 has a double latch configuration in which a latch operation is performed by a two-phase clock signal of CKA and CKB shown in FIG. 4, and includes a master latch 5M and a slave latch 5S. The data bus 4 is connected to the input side of the master latch 5M, and the output side of the master latch 5M is connected to the input side of the slave latch 5S. The output side of the slave latch 5S is connected to the data bus 4 via the output buffer 7.
[0008]
The AND gate 8 outputs a logical product signal of the decode signal TIER, the write signal output from the CPU 1 or 2 and the clock signal CKB to the master latch 5M as a latch signal. The clock signal CKA is directly given to the latch signal of the slave latch 5S. On the other hand, the AND gate 9 outputs a logical product signal of the decode signal TIER and the read signal output from the CPU 1 or 2 to the output buffer 7 as an enable signal (level).
[0009]
In the above multi-CPU system, a case where the TIER register 5 is accessed according to the timing chart shown in FIG. 5 will be described. The CPUs 1 and 2 operate in synchronization with the clock signal CKA. Assume that the initial value of the TIER register 5 is “00h (HEX)”. First, the CPU 1 starts a read-modify-write cycle (hereinafter referred to as an RMW cycle) at time T1, reads the data value of the TIER register 5 (slave latch 5S), and performs bit operation (sets the 0th bit to “1”). It is assumed that the data value “01h” of the operation result is written in the TIER register 5 at time T3. Then, data is written into the master latch 5M at the timing of the clock signal CKB after time T3.
[0010]
At this time, when another CPU 2 starts an RMW cycle at time T2, the CPU 2 reads the data value “00h” of the TIER register 5 at which time the bit operation result by the CPU 0 is not yet reflected at the time T2. A bit operation (set the fourth bit to “1”) is performed, and a data value “10h” as a result of the operation is written to the TIER register 5 at time T4.
[0011]
That is, if the CPU 2 starts an RMW cycle at time T4, the CPU 1 reads the data value “01h” of the TIER register 5 in which the bit operation result by the CPU 1 is reflected, and performs the bit operation. The data value written to the register 5 should be “11h”. However, if the CPU 2 executes the cycle during the execution of the RMW cycle by the CPU 1 as described above, the data in the TIER register 5 will not be as expected, resulting in hindering subsequent control.
[0012]
The present invention has been made in view of the above circumstances, and the purpose thereof is to determine the data value of a register regardless of the timing at which a plurality of CPUs perform a read-modify-write cycle on the same register. Is to provide a register control device that can be controlled so as to meet the expected value, and a multi-CPU system including the register control device.
[0013]
[Means for Solving the Problems]
According to the register control device of claim 1, for example, when any one of the CPUs executes a bit operation instruction and sets the data value of an arbitrary bit of the register to “0”, first, the read-modify In the read cycle of the first half of the write cycle (RMW cycle), the “0” setting register is accessed to read the data value of all the bits “1” (hereinafter referred to as all “1” data). Then, the data value of the change target bit is set to “0” in the read all “1” data, and then the write cycle is performed with the address of the “0” setting register. Then, the multiplexer outputs the data value “0” for the bit whose data value has been changed to “0” by the CPU, and outputs the data held in the register for the other bits. Select
[0014]
Also, when any CPU sets the data value of any bit in the register to “1”, the “1” set register is accessed in the read cycle of the first half of the RMW cycle, and the data of all the bits “0” is stored. A value (hereinafter referred to as all “0” data) is read. Then, the data value of the change target bit is set to “1” in the read all “0” data, and then the write cycle is performed with the address of the “1” setting register. Then, the multiplexer outputs the data value “1” for the bit whose data value has been changed to “1” by the CPU, and outputs the data held in the register for the other bits. Select
[0015]
That is, even if the CPU (B) starts the RMW cycle before the RMW cycle performed by the other CPU (A) is completed, the CPU (A) is still at the time when the latter write cycle is performed by the CPU (B). The RMW cycle is completed, and the data after the change is held in the register. Therefore, the data written to the register in the write cycle by the CPU (B) is the data changed by the CPU (A) for the bits that are not changed by the CPU (B). Therefore, even when a plurality of CPUs that are not designed to be applied to a multi-CPU system in advance access a register, it is possible to control the data value of the register to always be as expected.
[0016]
And In the condition that the multiplexer selects the output data of the CPU as the data to be output to the register,
Or (decode signal is a register)
Add Therefore, the CPU can perform not only setting by a bit operation on the register but also normal writing (that is, simultaneous writing of all bits) by outputting an address assigned to the register.
[0017]
Claim 2 According to the described multi-CPU system, the claims 1 By providing the above-described register control device, it is possible to configure a system that shares peripheral circuits such as registers using a CPU that is not designed to be applied in advance to a multi-CPU system.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below with reference to FIGS. 3 that are the same as those in FIG. 3 are denoted by the same reference numerals, description thereof is omitted, and only different portions will be described below. In this embodiment, two CPUs 1 and 2 are replaced with CPUs 11 and 12. The address bus 13 is connected to an address decoder 13 in place of the address decoder 6, and the data bus 4 is connected to a TIER register 14 in place of the TIER register 5 and two read-only registers TIER0W register (“0”). A set register 15 and a TIER1W register ("1" set register) 16 are connected.
[0019]
These registers 15 and 16 are assigned addresses different from those of the TIER register 14, respectively. The TIER0W register 15 performs an RMW cycle by the CPU 11 or 12 executing a bit manipulation instruction to the TIER register 14 and accesses when any of the 8 bits is set to “0”. In this case, the data value all “1” is output on the data bus 4.
[0020]
The TIER1W register 16 is set so as to be accessed when the CPU 11 or 12 similarly performs an RMW cycle on the TIER register 14 and sets “1” in any of the 8 bits. In this case, the data value all “0” is output on the data bus 4.
[0021]
That is, the TIER0W register 15 outputs the enable signal to the data output unit 15a that outputs all “1” data, the output buffer 15b that outputs the data on the data bus 4, and the output buffer 15b. An AND gate 15c is provided. The AND gate 15c calculates the logical product of the decode signal TIER0W output from the address decoder 13 and the read signal that the CPU 11 or 12 becomes active (high) when executing the read cycle, and outputs an enable signal for the output buffer 15b. It is like that.
[0022]
Similarly to the TIER0W register 15, the TIER1W register 16 also has a data output unit 16 a that outputs all “0” data, and an output buffer 16 b and an output buffer 16 b that output the data on the data bus 4. An AND gate 16c for outputting an enable signal is provided. The AND gate 16c calculates the logical product of the decode signal TIER1W output from the address decoder 13 and the read signal from the CPU 11 or 12, and outputs an enable signal for the output buffer 16b.
[0023]
In FIG. 1, the TIER register 14 shows only one bit cell 14B (i) having a configuration corresponding to one bit (i-th bit, i = 0 to 7), and actually eight bit cells 14B. (0) to 14B (7). Each bit cell 14B is mainly configured by connecting the data selection unit 17a of the multiplexer 17, the master latch 18, the slave latch 19, and the output buffer 20 in series from the data bus 4 side. The output terminal of the output buffer 20 is connected to the line D (i) of the data bus 4, and the output terminal of the slave latch 19 is connected to the other input terminal of the data selector 17a. The data selection unit 17a is configured to select one of the two input terminals based on the selection signal output from the selection signal generation circuit 17b and output the selected one to the master latch 18.
[0024]
The selection signal generation circuit 17b is supplied with three decode signals TIER, TIER0W, TIER1W output from the address decoder 13 and the i-th bit data D (i) of the data bus 4, and based on these input signals, the data The internal logic is configured so that the selector 17a selects input data and outputs it to the master latch 18 as follows.

If the conditions are other than the above, (Output data: Data held in slave latch 19)
The selection signal generation circuit 17b outputs, for example, a selection signal corresponding to the above two conditions (for example, a high level when the former is established and a low level when the latter is established) to the data selection unit 17a, The data selection unit 17a selects one of the two input terminals according to the selection signal.
[0025]
The latch signal of the master latch 18 is given by a 3-input AND gate 21. The input terminal of the AND gate 21 is supplied with a write signal that the CPU 11 or 12 becomes active (high) during execution of a write cycle, a B-phase signal CKB of a two-phase clock signal, and an output signal of the OR gate 22. Yes. Three decode signals TIER, TIER0W, and TIER1W output from the address decoder 13 are supplied to the three-input OR gate 22, respectively.
[0026]
Further, the A-phase signal CKA of the two-phase clock signal is directly given to the latch signal of the slave latch 19, and the output signal of the AND gate 23 is given to the output buffer 20 as an enable signal. The decode signal TIER output from the address decoder 13 and the read signal of the CPU 11 or 12 are given to the input terminal of the AND gate 23.
[0027]
The TIER register 14 is classified into a register unit (register) 14a and a register control unit 14b. The register unit 14 a is a part including a master latch 18, a slave latch 19, an output buffer 20, and AND gates 21 and 23, and the register control unit 14 b is a part including a multiplexer 17, an AND gate 21, and an OR gate 22.
[0028]
A register control unit 24 is configured by adding the address decoder 13, the TIER0W register 15, and the TIER1W register 16 to the register control unit 14b. Further, the register unit 14 a and the register control device 24 plus the CPUs 11 and 12 constitute a multi-CPU system 25.
[0029]
Next, the operation of this embodiment will be described with reference to FIG.
<1><When"1" is set in the TIER register 14 by a bit manipulation instruction>
For example, when the CPU 11 performs an RMW cycle to execute a bit operation for setting the 0th bit of the TIER register 14 to “1”, the CPU 11 does not operate on the TIER register 14 but on the TIER1W register 16. An RMW cycle is performed. Then, data 00h is read from the TIER1W register 16 at time T1. When the CPU 11 operates the internal register so that only the 0th bit of the read data is set to “1”, the CPU 11 outputs the address of the same TIER1W register 16 at time T3 and performs the write cycle of the data 01h.
[0030]
In this case, writing to the TIER1W register 16 that is a read-only register is not performed, and instead, the decode signal TIER1W is output and the output terminal of the OR gate 22 becomes high level. Therefore, at the rising timing of the clock signal CKB. The output terminal of the AND gate 21 also becomes high level, and data is written to the master latch 18 of the TIER register 14.
[0031]
In each of the bit cells 14B (0) to 14B (7), since the decode signal TIER1W is output, the data selection unit of the bit cell 14B (0) in which the data value “1” is output on the data bus 4 17a selects and outputs the data value “1” of the data bus 4 (D (0)) to the master latch 18 in accordance with the selection signal (high level) output from the selection signal generation circuit 17b.
[0032]
In the other bit cells 14B (1) to 14B (7), since the selection signal generation circuit 17b sets the selection signal to the low level, the data selection unit 17a selects and outputs the data held in the slave latch 19 to the master latch 18. . The data held in the slave latch 19 at this time is data 00h before being rewritten by the write cycle at time T3.
[0033]
That is, the bit data other than the bit that is set to “1” by the bit operation instruction of the CPU 11 is written by selecting the data held in the slave latch 19 regardless of the data that the CPU 11 outputs on the data bus 4. become. As a result, data 01h in which only the 0th bit of the data 00h is set to “1” is written into the master latch 18. The data in the slave latch 19 is updated to the same data 01h as the data written in the master latch 18 at the rising timing of the clock signal CKA after time T3.
[0034]
Therefore, similarly to the conventional example shown in FIG. 5, if another CPU 12 starts an RMW cycle at time T2, the CPU 12 reads the data value “00h” of the TIER1W register 16 at time T2 and performs bit operation ( The fourth bit is set to “1”), and the data value “10h” of the operation result is written to the address of the TIER1W register 16 at time T4.
[0035]
Then, the data selection unit 17a of the bit cell 14B (4) whose data value “1” is output on the data bus 4 selects and outputs the data value “1” to the master latch 18 by the same process as described above. The data selection units 17a of the other bit cells 14B (0) to 14B (3) and 14B (5) to 14B (7) select and output the data held in the slave latch 19 to the master latch 18.
[0036]
That is, when the CPU 12 performs a write cycle in the latter half of the RMW cycle at time T4, the RMW cycle by the CPU 11 is completed. Accordingly, since the data held in the slave latch 19 has been updated to 01h, the data 11h in which the fourth bit of the 01h data is changed to “1” is written in the master latch 18 (8 bits) of the TIER register 14. become.
[0037]
<2><When “0” is set in the TIER register 14 by a bit manipulation instruction>
For example, when the initial value of the TIER register 14 is 77h and the CPU 11 performs an RMW cycle to execute a bit operation for setting the 0th bit of the TIER register 14 to “0”, An RMW cycle is performed for the TIER0W register 15. Then, the data FFh is read from the TIER0W register 15 at time T1. When only the 0th bit is set to “0” at time T2, the CPU 11 outputs the same address of the TIER1W register 16 at time T3 and performs a write cycle of the data FEh.
[0038]
In this case, since the decode signal TIER0W is output and the output terminal of the OR gate 22 becomes high level, the output terminal of the AND gate 21 also becomes high level at the rising timing of the clock signal CKB, and the master latch 18 of the TIER register 14 Data is written to
[0039]
In each of the bit cells 14B (0) to 14B (7), since the decode signal TIER0W is output, the data selection unit of the bit cell 14B (0) in which the data value “0” is output on the data bus 4 17a selects and outputs the data value “0” of the data bus 4 (D (0)) to the master latch 18, and the other data selection units 17a of the bit cells 14B (1) to 14B (7) The data held in the slave latch 19 is selected and output.
[0040]
Therefore, also in this case, for the bit data other than the bit set to “0” by the bit operation instruction of the CPU 11, the data held in the slave latch 19 is selected regardless of the data output from the CPU 11 onto the data bus 4. Will be written. Since the data held in the slave latch 19 is 77h, when the 0th bit is set to “0”, the data written to the master latch 18 of the TIER register 14 becomes 76h.
Needless to say, even if the above-described process is performed by changing the access order of the CPUs 11 and 12, the same result is obtained.
[0041]
(3) <When reading data from the TIER register 14 by a read cycle>
For example, when the CPU 11 simply reads the data in the TIER register 14, the CPU 11 performs a read cycle on the TIER register 14 as usual. Then, since the address decoder 13 outputs the decode signal TIER, the output terminal of the AND gate 23 becomes high level. Since the output buffer 20 is enabled, the data held in the slave latch 19 is output onto the data bus 4.
[0042]
(4) <When writing arbitrary data to the TIER register 14 by a write cycle>
For example, when the CPU 11 writes data 00h to the TIER register 14, a write cycle is performed on the TIER register 14 as usual. Also in this case, since the address decoder 13 outputs the decode signal TIER, the selection signal generation circuits 17b of all the bit cells 14B output high level selection signals. Therefore, the data selection unit 17 a selects the data on the data bus 4 output by the CPU 11 and outputs it to the master latch 18.
[0043]
Then, the output terminal of the OR gate 22 becomes high level, and the output terminal of the AND gate 21 also becomes high level at the rising timing of the clock signal CKB, so that the data 00h is written in the master latch 18 of the TIER register 14.
[0044]
As described above, according to the present embodiment, when the CPU 11 executes a bit manipulation instruction and sets the data value of an arbitrary bit in the TIER register 14 to “1”, the TIER1W register 16 in the read cycle in the first half of the RMW cycle. Is read, the data value of the change target bit is set to “1”, and a write cycle is performed with the address of the TIER1W register 16, the multiplexer 17 sends the data value to the master latch 18 of the TIER register 14. The data value “1” is output for the bits changed to “1”, and the data held in the slave latch 19 is selected for the other bits.
[0045]
When the CPU 11 sets the data value of an arbitrary bit in the TIER register 14 to “0”, in the read cycle in the first half of the RMW cycle, the data is read by accessing the TIER0W register 15 and the data value of the change target bit is set. When a write cycle is performed with the address of the TIER0W register 15 after setting it to “0”, the multiplexer 17 outputs the data value “0” for the bit whose data value has been changed to “0” to the master latch 18. The other bits are selected so that the data held in the slave latch 19 is output.
[0046]
That is, even if another CPU 12 starts the RMW cycle before the RMW cycle performed by the CPU 11 is completed, the RMW cycle by the CPU 11 is completed at the time when the latter write cycle is performed by the CPU 12, so that after the change Are held in the slave latch 19. Therefore, the data written to the master latch 19 in the write cycle by the CPU 12 is the data changed by the CPU 11 for the bits that the CPU 12 did not change. Therefore, the data value of the TIER register 14 accessed by a plurality of CPUs is always changed. It can be controlled to be as expected.
[0047]
In addition, according to the present embodiment, in the selection signal generation circuit 17b, “or (decode signal is a register)” is also added to the condition for the data selection unit 17a to select the data D (i) as the output data. The CPU 11 or 12 not only sets the TIER register 14 by bit operation, but also outputs an address assigned to the TIER register 14 and writes normal arbitrary data (simultaneous writing of all bits). You can also.
[0048]
In addition, since the register control device 24 is provided, a multi-CPU system that shares peripheral circuits such as the TIER register 14 even with the CPUs 11 and 12 that are not designed to be applied to a multi-CPU system in advance. 25 can be configured.
[0049]
The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following modifications or expansions are possible.
The present invention is not limited to single-bit bit operations, and can be similarly applied to a case where a plurality of bit operations (so-called bit field operations) are performed.
The data bus size is not limited to 8 bits, but may be 4 bits, 16 bits, or 32 bits.
The register is not limited to the control register but may be a data register. Further, the register may be configured using a D flip-flop that operates in synchronization with the operation clock of the CPU, without being limited to the TIER register 14 having a double latch configuration.
For example, the read signal and the write signal may be a single signal (read / write signal) indicating a read cycle when it is at a high level and a write cycle when it is at a low level. In this case, a read / write signal may be given to the corresponding input terminal of the AND gate 21 via an inverter gate, or the input terminal may be set to negative logic.
[0050]
The present invention may be applied to a system having three or more CPUs.
Ma The entire multi-CPU system may be configured as an integrated circuit device on a semiconductor substrate, or may be configured as a circuit device in which each individual discrete element is mounted on a printed circuit board.
[Brief description of the drawings]
FIG. 1 is a diagram showing an electrical configuration centering on a TIER register according to an embodiment of the present invention.
FIG. 2 is a timing chart showing changes in the data value of the TIER register when two CPUs perform a read-modify-write cycle.
FIG. 3 is a diagram corresponding to FIG.
FIG. 4 is a diagram showing a waveform of a two-phase clock signal
FIG. 5 is a view corresponding to FIG.
[Explanation of symbols]
11 and 12 are CPUs, 13 is an address decoder, 14 is a TIER register, 14a is a register unit (register), 14b is a register control unit, 15 is a TIER0W register (register for “0”), and 16 is a TIER1W register (“1”) "Set register", 17 is a multiplexer, 18 is a master latch, 19 is a slave latch, 24 is a register controller, and 25 is a multi-CPU system.

Claims (2)

In a register controller for controlling the data value of a register accessed by a plurality of CPUs performing a read-modify-write cycle ,
“0” setting register that is accessed when any CPU sets the data value of any bit of the accessed register to “0” during a read operation, and the data value “1” of all bits is read When,
"1" set register that is accessed when any CPU sets the data value of any bit of the accessed register to "1" during a read operation, and the data value "0" of all bits is read When,
An address decoder that decodes an address output by the CPU and outputs a decode signal;
Each of the registers to be accessed at the time of a write operation is arranged on the input side of the register to be accessed, based on the decode signal output by the address decoder and the output data at the time of the write operation of the read / modify / write cycle of the CPU. A multiplexer that selects and outputs the output data for each bit according to the following conditions,
{(The register to which the decode signal is accessed)}
Or {(decode signal is a register for setting “0”)
(CPU output data is “0”)}
Or {(decode signal is a register for setting “1”)
And (CPU output data is “1”)}
Then, (output data is CPU output data),
If the conditions are other than the above, (Output data is the data held in the accessed register)
Write to the accessed register when the CPU outputs the address of the accessed register, “0” set register or “1” set register to perform a read-modify-write cycle It is configured to write data during operation ,
In the condition that the multiplexer selects and outputs the output data of the CPU when performing a write operation in a case other than the read-modify-write cycle for the accessed register,
Or (the register to which the decode signal is accessed )
Add
Register that is the access, even when writing by outputting the address of the register that the CPU is the access register control apparatus characterized by being configured so that data is written.   A multi-CPU system comprising the register control device according to claim 1.

Images