JPS5999551A - Address generating circuit - Google Patents

Abstract

PURPOSE:To select externally a register by providing a logical circuit which inputs a selection signal from an instruction decoder and a modifying signal for segmentation supplied from outside of an LSI chip to a segment base register selecting circuit. CONSTITUTION:A combinational logical circuit 6 is provided between the instruction decoder 1 and a multiplexer 3. Segment base registers 2-1-2-n are connected to the multiplexer 3. A necessary segment inside deviation address signal 12 is sent according to the kind of an instruction once the instruction decoder 1 outputs the segment base register selection signal 11, and the signal 12 is stored in an address register 4. The segmentation modifying signal 17 from outside of the circuit allows the combinational logical circuit 6 to convert the selection signal from the instruction decoder 1. Consequently, the generation process of a physical address from an adding circuit is controlled externally.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an address generation circuit for a segmentation mechanism of a microprocessor.

Conventional configurations and their problems In recent years, the scope of application of microprocessors has expanded, and as a result, efforts have been made to improve the functionality of microprocessors. The main memory access function using a segmentation method, which was one of the functions of conventional minicomputers or mainframe computers, has also been incorporated into a single chip LSI (Large Scale Integrated Circuit).

FIG. 1 shows a conventional example of an address generation circuit in a segmentation mechanism of a microprocessor. In the figure, 1 is an instruction decoder, 2-1 to 2-n are segment base registers that store segment base addresses, and 3 is one segment base register according to a segment base selection signal 11 sent from the instruction decoder 1. 4 is an address register for storing the intra-segment deviation, and 5 is an adder circuit which receives the output of M/l and f plexer 3 and the output of address register 4 and outputs a physical address.

The operation of the above configuration will be described below. First, a processor that has fetched an instruction from main memory interprets the instruction using instruction decoder 1, and as a result, when access to main memory or input/output area is required, it should be selected according to the type of instruction. Segment base register 2-1゜2-2. ...2-n, the segment base register selection signal 11 is output.

At the same time, the instruction decoder 1 outputs a necessary intra-segment deviation address signal 12 according to the type of instruction, and stores it in the address register 4. The segment base registers 2-1 selected by the multiplexer 3 by the adder circuit 5...
- The contents of one of the segment base registers 2-n and the contents of the address register 4 are added to generate a real address of the main memory or input/output area, that is, a physical address 13.

Even when the command is set to 7, the above operation is executed as Mar f 7.
” It is exactly the same except that the register selected by the lexer 3 is the segment base register corresponding to the segment containing the instruction code, and the contents of the address register 4 are the same as the contents of the instruction counter.

These segmentation mechanisms have been incorporated entirely into a single-chip microprocessor as LSIs become more highly integrated; Only the physical address added by circuit 5 is output. In a microprocessor that has a segmentation mechanism with this structure, all physical address generation is uniquely determined by the instruction code, and the address generation mechanism cannot be controlled from outside the LSI chip. Microprocessors with conventional segmentation capabilities in a single chip LS1 can only be used in a uniform manner, making it difficult to realize multiprocessor configurations, main memory management, and expansion of program areas.

OBJECTS OF THE INVENTION In view of the above two drawbacks, it is an object of the present invention to enable flexible application of a microprocessor incorporating a segmentation mechanism.

Structure of the Invention The present invention provides a segment base register selection circuit with a combinational logic circuit that receives as input a selection signal from an instruction decoder and a segmentation modification signal applied from outside the LSI chip. By configuring the segment base register to be selected by modifying signals,
This aims to achieve the above objectives.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows the configuration of the address generation circuit in the first embodiment of the present invention. In FIG. 2, 1 is an instruction decoder, 2-1, 2-2, 2-3..., 2-
ntrl segment base register, 3 is a multiplexer, 4 is an address register, and 5 is an adder circuit, which is the same as the configuration shown in FIG.

The difference from the configuration shown in FIG. 1 is that a segment base register selection signal 11 sent from an instruction decoder 1 and a segment control signal supplied from outside the processor are input, and a \JIJ groan signal 14 is given to a multiplexer 3. The point is that a combinational logic circuit 6 is newly provided.

The operation of the address generation circuit of this embodiment configured as described above will be explained below.

First, the processor fetches an instruction from the main memory using a program execution mechanism (not shown in FIG. 2), and the instruction is interpreted by the instruction decoder 1. At that time, a read or write operation to the main memory or input/output area is required. If so, the instruction decoder 1 outputs a segment base register selection signal 11 to be selected depending on the type of instruction. At the same time, the instruction decoder 1 outputs a necessary intra-segment deviation address signal 12 depending on the type of instruction, and stores it in the address register 4. The above operation is as explained in the conventional example. On the other hand, a combinational logic circuit 6 which receives as input a segmentation modification signal 17 and a segment base register selection signal 11 supplied from outside the circuit has a multifunction logic circuit 6 which selects one of the plurality of segment base registers 2-1 to 2-H. A control signal 14 to the plexer 3 is output. the value of one register among the plurality of segment base registers 2-1 to 2-n selected by the multiplexer 3;
That is, the segment base address is applied to the adder circuit 6 via the signal line 16. The adder circuit 5 receives a signal 1 indicating the intra-segment deviation address from the address register 4.
6 and the segment base address of the signal 15 mentioned above are added to output the physical address 13.

As described above, according to this embodiment, the segment base/register selection signal 11 supplied from the instruction decoder is input from outside the circuit in order to select one of the plurality of segment base registers 2-1 to 2-n. To enable the physical address generation process to be controlled from outside the segmentation mechanism by a combinational logic circuit 6 provided to convert the supplied segmentation modification signal 17 into a selection signal different from the original one. I can do it.

FIG. 3 is a diagram configuring a multiprocessor system using the circuit shown in FIG. 2.

In FIG. 3, 1 is an instruction decoder, 2-1 to 2-n are segment base registers, 3 is a multiplexer, 4 is an address register, and 5 is an adder circuit.

Reference numeral 6 denotes a combinational logic circuit, which has the same configuration as that shown in FIG. 7-1. 2 is a one-chip LSI microprocessor including the address generation circuit shown in the first embodiment of the present invention; 8 is a microprocessor that executes an operating system program; and 9
1 is a main memory, 10 is a flip-flop which is internally controlled by the microprocessor 8 and controlled by a program, and 20 is a common bus line including an address information line.

The operation of the multi-procerana system configured as described above will be explained below. ◇ The microprocessor 8 runs the flip-flop 10 by a program execution mechanism not shown in the figure.
When set to 1, the logic ss1tt is applied to the combinational logic circuit 6 in the other microprocessor 7-2, and the logic 60 is inverted by the inverter 21 to the microprocessor 7-2. (l'l: Input.

For the sake of explanation, assume the truth table shown in FIG. 4 as an example of the combinational logic circuit 6. In FIG. 4, if the segment base register selection signal generated from the instruction decoder indicates segment base register 2-1,
Segmentation modification signals are both logic N○〃 and logic X
Even when X1, the output is segment base register 2-1
However, if segment base register 2-2 is input as a segment base register selection signal, the output will differ depending on the segmentation modification signal. That is, the segmentation modification signal 17 is logical
When the logic is \O, a signal specifying the segment base register 2-1 is output, and when the logic is \\1, a signal specifying the segment base register 2-3 is output.

When a signal specifying the segment base registers 2-3 is input, the segment base registers 2-3 . A signal specifying segment pace register 2-2 is output. A microprocessor 7- having an aiming logic circuit 6 having such a configuration
1. ．． When logic \\1 and logic \\0 // are input to 7-2 as segmentation modification signals as described above, respectively, these two microprocessors 7 receive the same segment base register selection signal 11 from the instruction decoder 1. Even if the segment base registers 2-1 to 2-n are output, the multiplexer 3 selects different segment base registers 2-1 to 2-n. Assuming that a signal to select the segment base register 2-2 is now output from the convergence decoder 1, the adder circuit 5 of the microprocessor 7-1 adds the intra-segment deviation address to the contents of the segment base register 2-3. Output. Microprocessor Noza 7-2
Since the physical address obtained by adding the intra-segment deviation address to the contents of segment base register 2-2 is output from 2-2, two microprocessors can specify the same segment base register by program on the main memory while using different main memories. area can be accessed.

As explained above, segment access information, which is originally uniquely determined by instruction decoding, can now be changed by external circuits, especially the microprocessor that executes the operating system, making it possible to configure flexible multiprocessor systems. can.

In addition, in the explanation using FIG. 3, the microprocessor 7
The segmentation modification signals input to -1 and 7-2 are 1-bit information, which are mutually inverted information, but this is multi-bit/node information, and the microprocessor that executes the operating system transmits these to each microprocessor. By applying the signals independently to the built-in combinational logic circuits 6, it becomes possible to allocate the area of the main memory used by each processor, and a simple memory management function can be realized.

A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 6 1d is a diagram showing the configuration of an address generation circuit showing a second embodiment of the present invention. In the figure, 1 is an instruction decoder, 2'-1 to 2'-3 are segment base registers, 3 is a multiplexer, 4 is an address register, and 6 is an adder circuit, which is the same configuration as in Figure 2. . 6′
is a combinational logic circuit constituted by logic elements 6'-1 to 6'-4. Incidentally, FIG. 6 shows a truth table of the combinational logic circuit 6' in the second embodiment of the present invention.

The operation of the address generation circuit configured as described above will be explained below. A 2-bit segment base register selection signal 11-0.11-1 is output from the instruction decoder 1 and input to the combinational logic circuit 6'. The function of the combinational logic circuit 6' is the truth value shown in FIG. As shown, segment base registers 2'1. Segment base register 2'-2 selects segment base register.
When specified by signals 11-0 and 11-1, it is not affected by the segmentation modification signal 17 and the segment base register! Only when -3 is selected does the logic 1111 not access segment base register 2'-3, but access another segment base register via segmentation modifier signal 17. That is, the segmentation modification signal 17 is the logic SS
□ If //, access segment base register 2'-1; if logic SS1//, access segment base register 2'-2. This logic consists of an inverter 6-1.6-4 and an AND element 6-2.6 as shown in FIG.
-3.

In a microprocessor having a built-in address register configured as described above, the contents of the main memory at the address indicated by the internal register R1 of the microprocessor not shown in FIG.
When executing an instruction such as transferring data to memory 2', segment base register selection signals 11-0 . 11
-1 is output. Then segmentation modification signal 1
7 switches between using segment base register 2'-1 as a segment base address and using segment base register 2'-2. Therefore, if we allocate a segment in which a program is stored in segment base register 2'-1 and a segment to be a data area in segment base register 2'-2, then It can be switched by the segmentation modification signal 17 whether the address is taken on the program storage segment or on a segment that is another data area. In this way, if the program and data parts are combined into one segment, the segmentation modification signal 17 can be set to
If the program capacity is so large that the sum of the data part cannot fit into one segment, the segment modification signal 17 is set to logic \\1. The program part and the data part can be divided into separate segments to allow larger programs to be created.

As described above, by configuring the combinational logic circuit so that when a specific segment base register is selected, a segment base register other than the above-mentioned specific segment base register is selected by an external segmentation modification signal, the program area can be easily expanded.

Effects of the Invention As described above, the present invention provides a segmentation system comprising a plurality of segment base registers, a multiplexer for selecting one of the segment base registers, an address register for storing an intra-segment deviation address, and an adder circuit. By providing the mechanism with a combinational logic circuit that converts the segment base register selection signal from the instruction counter into another segment pace register selection signal by means of an externally supplied segmentation modification signal, the physical address generation process is external to the segmentation mechanism. can be more controlled and as a result L
A segmentation mechanism suitable for SI can be realized, and its effects are significant.

[Brief explanation of drawings]

FIG. 1 is a block wiring diagram of an address generation circuit using a conventional segmentation mechanism, FIG. 2 is a block wiring diagram of an address generation circuit according to a first embodiment of the present invention, and FIG.
The figure is a block wiring diagram configuring a multi-procerana system using the address generation circuit of Figure 2, Figure 4 is a diagram showing the truth value of the matching logic circuit of Figure 3, and Figure 5 is a diagram showing the truth value of the matching logic circuit of Figure 3. FIG. 6 is a block diagram of the address generation circuit in the second embodiment, and is a diagram showing truth values of the matching logic circuit of FIG. 1...Instruction decoder, 2-1, 2-2.2-
3;=2−n. 2'-1, 2'-2, 2'-3... Segment base register, 3... Multiplexer, 4
... Address register, 5 ... Addition circuit, 6 ... Combinational logic circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person33 Figure 3-340- Figure 4

Claims (2)

[Claims] (1) Combinational logic that inputs and combines an instruction decoder of a processor, a plurality of segment base registers, a selection signal output from the instruction decoder for selecting the segment base register, and a segment control signal supplied from outside the processor. a multiplexer circuit that selects one of the segment base registers according to the output of the combinational logic circuit; an address register that stores the intra-segment deviation; and a memory address that receives the output of the multiplexer and the output of the address register as inputs. An address generation circuit comprising an adder circuit that outputs a signal. (2) The combinational logic circuit is characterized in that when a specific segment base register is selected from a plurality of segment base registers by the instruction decoder, a segment base register other than the above-mentioned specific segment base register is selected by a segmentation modification signal. An address generation circuit according to claim 1.