JPH033047A - Memory with arithmetic function - Google Patents

Abstract

PURPOSE:To execute the processing of respective data in a memory in parallel in each chip by providing respective ports for inputting an address signal, for inputting and outputting a data signal, for inputting a read/write signal, and for inputting a mode signal and including an operation part into a memory chip. CONSTITUTION:The control part 10 inputs a data signal 100, a mode signal 101 and a read/write signal 102 from the external. When a memory mode is specified, the data signal 100 and the read/write signal 102 are respectively connected to a memory data signal 104 and a write enable signal 105 to access the memory 11 from the external. When a processing mode is specified by the mode signal 101, the memory data signal 104 is connected to an arithmetic data signal 106, the value of the data signal 100 is decoded, the values of the write enable signal 105 and an instruction code signal 107 are determined, and the arithmetic part 12 executes the operation of data stored in the memory 11. Thus, the operation of the data stored in the memory 11 can rapidly be executed.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a memory with arithmetic functions.

(Conventional technology) As one of the means to achieve high-speed processing in computers at the architectural level, so-called multiprocessor-type parallel processing technology that uses multiple gross processing elements consisting of processors and memory is used. is used.

(Problems to be Solved by the Invention) Multiprocessor systems generally require dedicated interfaces, monitors, etc. due to the difference in architecture from single processor systems. Therefore, it is necessary to create and debug software while being aware of the features unique to multiprocessors, and this poses a problem in that it is more difficult to handle than a single processor.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to incorporate an arithmetic unit into a memory chip so that processing of data in each memory can be executed in parallel for each chip, and can be implemented using the same interface as a normal memory chip. The objective is to provide a memory with arithmetic functions that can be used.

(Means for Solving the Problems) A memory with an arithmetic function according to the present invention includes ports for address signal input, data signal input/output, read/write signal input, and mode signal input, and includes a memory section, an arithmetic section, and a control section. If the mode signal is a memory mode, the control section controls the read/write mode.
According to the write signal, read or write to the memory using the address signal as an address and the data signal as data, and if the mode signal is a processing mode, only when the read/write signal is a write, Inputting data read from the memory using the address signal as an address to the arithmetic unit, decoding the data signal and specifying an operation in the arithmetic unit,
The calculation result from the calculation section is written into the memory using the address signal as an address.

(Operation) In addition to the input signals required by a normal memory, the device of the present invention inputs a new mode signal, thereby specifying one of the memory mode and the processing mode. In memory mode, only normal memory accesses are performed.

In the processing mode, it decodes the data signal and specifies read/write to the memory, calculation to the arithmetic unit, etc.
Perform operations on data stored in memory.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a memory with an arithmetic function according to the first invention.

The control unit 10 inputs a data signal 100, a mode signal 101, and a read/write signal 102 from the outside. There are two modes: a memory mode and a processing mode designated by the signal 101.

When memory mode is specified, data signal 100 and read/write signal 102 are transferred to memory data signal 104.
and a write enable signal 105, respectively, to access the memory 11 from the outside.On the other hand, the mode signal 101 sets the processing mode, and the read/write signal 1
When write is specified by 02, the memory data signal 104 and the calculation data signal 106 are connected, the value of the data code 100 is decoded, the write enable 7 is executed, and the signal 105 is
and the value of the instruction code signal 107, and the arithmetic unit 12 executes the arithmetic operation on the data stored in the memory 11.

This module will be explained later using FIG.

The memory 11 uses an address signal 103 from the outside as an address to read or write data to a memory data signal 104. Switching between read and write is designated by a write enable signal 105.

The calculation unit 12 inputs the calculation data signal 106 and the instruction code signal 107 output from the control unit 10, and calculates the instruction code signal 107 for the data of the calculation data signal 106.
The arithmetic unit 12, which executes the operation specified by 0 and t and outputs the result again to the signal 106, has a built-in register that holds each operand and the operation result, and these operations are also controlled by the instruction code signal 107. It shall be possible to specify. It is also assumed that execution of each instruction ends within a write cycle given by the read/write signal 102.

FIG. 2 is a block diagram showing an embodiment of the control section 10 included as one module in FIG. 1.

The data selector 22 selects one of the data signal 100 and the calculation data 106 according to the mode signal 101,
Connection with the memory data signal 104 is made, and in the case of the memory mode, the data signal 100 is selected, and in the case of the processing mode, the operation data signal 106 is selected.

The decoder 21 inputs the data signal 100, decodes it, and outputs it as a signal 200 and a signal 107. In FIG. 8, the data signal 100 is 8 bits, the signal 200 is 1 bit,
An example of a decoding table when the signal 107 is 3 bits is shown.

The logic circuit 20 inputs the read/write signal 102, the output signal 200 of the decoder 21, and the mode signal 101, executes a logical operation, and outputs the result as a write enable signal 105. For example, the read/write signal 102 has the value "0".
1” is read, value “0” is write, signal 200 is value “1”
'° is active, the value "1" of the mode signal 101 represents the processing mode, and the value "0" represents the memory mode.
The value of the write enable signal 105 is as follows.

Signal 105=Signal 102 0R (Signal 200ANO signal 101) In the present invention, read/write to the memory 11, instruction code for the arithmetic unit 12, etc. are used as the data signal 100.
Since it can be specified using , processing can be executed through an interface similar to normal memory. Further, the only signal newly required for a normal memory is the mode signal 101.

Next, FIG. 3 is a block diagram showing an embodiment of a memory with an arithmetic function according to the second invention. The following description will be made with reference to FIG. 3, however, since the memory 11 is exactly the same as that in FIG. 1, the description will be omitted.

In addition to the input signal of the control unit 10 shown in FIG.
Furthermore, a status signal 108 is input.

In the case of the memory mode and the case where writing is specified by the read/write signal 102 in the processing mode, the operation is exactly the same as that of the control section 10.

On the other hand, in the processing mode, the read/write signal 102
When read is designated by , the data signal 100 and the status signal 108 are connected, and the status of the arithmetic unit 32 can be read from the outside. This module will be explained later using FIG. 4.

The calculation unit 32 has the same functions as the calculation unit 12, and also outputs status information such as overflow and zero detection when executing calculations using the signal 1.
Output as 08.

FIG. 4 is a block diagram showing an embodiment of the control section 30 included as one module in FIG. A description will be given below with reference to FIG. 4, however, since the logic circuit 20 and decoder 21 are exactly the same as in FIG. 2, their description will be omitted.

The logic circuit 43 inputs the mode signal 101 and the read/write signal 102, executes a logical operation, and outputs the result as a signal 201.
Output as . For example, the signal 201 has a value of "0" if it is in memory mode, a value of "1" if it is in processing mode and read is specified, and a value of "2" if it is in processing mode and write is specified. .

The data selector 42 is a 2×2 changeover switch, and according to the output signal 201 of the logic circuit 43, the signal 100,
106 and the signals 104 and 108. When the value of the signal 201 is "ON," the data signal 1 from the outside is
00 and the memory data signal 104 are connected, and the memory 1
Only access to 1 is made. The value of signal 201 is “
1″, the signal 108 representing the status of the calculation unit 32
and a data signal 100 from the outside are connected, and the status is read out. When the value of the signal 201 is “2”, the memory data signal 104 and the calculation data signal 106
are connected, and operations are performed on data stored in the memory 11.

Next, FIG. 5 is a block diagram showing an embodiment of a memory with an arithmetic function according to the third invention.

The following explanation will be given with reference to FIG. 5, but since the memory 11 and the calculation section 12 are exactly the same as in FIG. 1, their explanation will be omitted.

In addition to the input signal of the control unit 10 shown in FIG.
Furthermore, an address signal 103 is input.

Regarding the memory mode, the operation is exactly the same as that of the control section 10. In the processing mode, the arithmetic section 12 operates not only on the data stored in the memory 11 but also on the address signal 10.
It is also possible to perform calculations on data represented by 3. This makes it possible to perform operations on literal data given as address signals.

FIG. 6 is a block diagram showing an embodiment of the control section 50 included as one module in FIG.

The following description will be made with reference to FIG. 6, but the logic circuit 20
Since the details are exactly the same as those in FIG. 2, the explanation will be omitted. Further, here, the address signal 103 is the signal 100,
It is assumed that the signal has the same bit width as the signal representing data such as 103 and 104.

The logic circuit 63 inputs the mode signal 101 and the output signal 600 of the decoder 61, performs a logical operation, and outputs the result as the signal 6.
Output as 01. For example, the signal 601 is “0” in the memory mode, and the value of the signal 600 is “0” in the processing mode.
If it is "0", the value is "1", and if it is the processing mode and the value of the signal 600 is "1", the value is "2".

The data selector 62 is a 2×2 changeover switch similar to the data selector 42 in FIG.
4,103, the value of signal 601 is “
When the value of the signal 601 is "1", the external data signal 100 and the memory data signal 104 are connected, and only the memory 11 is accessed. When the value of the signal 601 is "1", the address signal 103 and the operation data signal 106 are connected. are connected,
Operations are performed on literal data. signal 601
When the value of is "2'', the memory data signal 104 and the operation data signal 106 are connected, and the operation on the data stored in the memory 11 is executed.

Decoder 61 receives data signal 100 and decodes it to generate signals 200, 107.600. In FIG. 9, the data signal 100 is 8 bits, the signal 200 is 1 bit,
In FIG. 9, which shows an example of a decoding table when the signal 107 is 3 bits and the signal 600 is 1 bit, when specifying an operation on literal data, the value of the signal 600 is "
0" When specifying an operation on data stored in the memory 11, the data signal 100 is applied from the outside so that the value of the signal 600 becomes "1."

The overall configuration of the memory with operations according to the fourth invention is completely the same as that shown in FIG. 1, so the explanation will be omitted.

Next, FIG. 7 is a block diagram showing an embodiment of the control section 10 included as one module in the memory with arithmetic function of the fourth invention. The following explanation will be given with reference to FIG. 7, but regarding the logic circuit 20 and data selector 22,
Since it is exactly the same as the figure, the explanation will be omitted.

Decoder 70 receives data signal 100 and decodes it to generate signals 700 and 701. In FIG. 10, the data signal 100 is 8 bits, the signal 700 is 5 bits, and the signal 7 is 8 bits.
An example of a decoding table when 01 is 3 bits is shown.

The sequencer 71 is configured to include a memory for storing instruction codes in advance, an address generation unit for the memory, and the like. The signal 700 output from the decoder 70 is set as the initial value of the address, and the signal 701 is set as the number of generated addresses (i.e., the number of instruction steps), and a series of instruction codes are read from the built-in memory and output to the signals 200 and 107. do. This allows the calculation unit 12 to execute a series of calculations on the data stored in the memory 11.

FIG. 11 shows an example of a device including four memories with arithmetic functions according to the present invention.

Performance x, memo with function IJII0.111, 112゜11
3 is the data signal 100. read/write signal 102,
The address signal 103 is common to each, and mode signals 1100 to 1103 are input individually.

For example, when executing the operation C+ −−At +B+ (0≦1≦15) using these, first, in the module 110, Ao ~As, Bo ~Bs, module 111
niA, ~AT, 84~B? , A to module 112
Az, Ba~B 11, A 12~ in module 113
A Is and 812 to B Is are stored in addresses 0 to 7, respectively.Primary mode signals 1100 to 110 are used as processing mode, read/write signal 102 is used as write, and addition to the data stored at the above addresses is used as data. signal 10
If specified using 0, the above calculation can be executed by parallel processing of four modules. Note that the mode signal can be a flip-flop output that can be set from a bus consisting of signal selections 100, 102, and 103, or a part of the address signal 103. In that case, the bus signal line is the same as in a system using conventional memory. That's fine.

In contrast to the first invention, the second and third inventions. The functions added in the fourth invention are all independent functions, and it is also possible to use them in combination.

(Effects of the Invention) As explained above, in the memory with an arithmetic function of the present invention, not only can operations be performed on data stored in the memory at high speed, but also instruction codes etc. for the arithmetic unit can be specified by data signals. Therefore, an interface similar to that of normal memory can be used. This has the effect of greatly reducing the burden of creating software, and also allows an existing memory system to be easily changed to a parallel processing system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a memory with an arithmetic function according to the first invention, FIG. 2 is a block diagram showing a control section 10 included as one module in the first invention, and FIG. FIG. 4 is a block diagram showing an embodiment of the memory with arithmetic function according to the second invention, FIG. 4 is a block diagram showing the control section 10 included as one module in the second invention, and FIG.
FIG. 6 is a block diagram showing a control unit 10 included as one module in the third invention, and FIG. 8 is a block diagram showing an example of a decoding table in the decoder 21 included as one module in FIG. 2, and FIG. 9 is a block diagram showing the decoder 61 included as one module in FIG. 6. FIG. 10 is a diagram showing an example of a decoding table in the decoder 70 included as one module in FIG. 7, and FIG. 11 is a diagram showing an example of a decoding table in the decoder 70 included as one module in FIG. FIG. 10.30.50...Control unit, 11...Memory, 1
2.32... Arithmetic unit, 20.43. ．． 63...Logic circuit, 21.61.70...Decoder, 71...Sequencer, 110,111,112.113...Memory with arithmetic function of the present invention. Figure 3 Figure 4 Figure 7 Figure 8 Figure 9

Claims (4)

[Claims] (1) Consists of a memory section, an arithmetic section, and a control section, and includes ports for address signal input, data signal input/output, read/write signal input, and mode signal input; mode, the read/
According to the write signal, read or write to the memory using the address signal as an address and the data signal as data, and if the mode signal is a processing mode, only when the read/write signal is a write, Inputting data read from the memory using the address signal as an address to the arithmetic unit, decoding the data signal and specifying an operation in the arithmetic unit,
A memory with an arithmetic function, characterized in that an arithmetic result from the arithmetic unit is written into the memory using the address signal as an address. (2) The control unit reads the status of the arithmetic unit only when the mode signal is a processing mode and the read/write signal is a read mode. Memory with arithmetic functions as described in section. (3) If the mode signal is a processing mode, the control unit decodes the data signal only when the read/write signal is a write, and inputs the address signal as data input to the calculation unit. Selecting either data read from the memory or the address signal as an address, specifying an operation in the arithmetic unit, and sending an arithmetic decision from the arithmetic unit to the memory using the address signal as an address. 2. The memory with an arithmetic function according to claim 1, wherein the memory has an arithmetic function. (4) The control unit includes the memory and a sequencer that stores instruction codes for the arithmetic unit in advance, and if the mode signal is a processing mode, only when the read/write signal is a write. Then, according to the result of decoding the data signal, a series of instruction codes are read from the sequencer, and the data read from the memory using the address signal as an address is input to the arithmetic unit, and the arithmetic operation in the arithmetic unit is performed. 2. The memory with an arithmetic function according to claim 1, wherein the memory with an arithmetic function performs designation and writes an arithmetic result from the arithmetic unit using the address signal as an address into the memory.