JPS6246891B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an instruction decoder circuit in a microcomputer.

An example of the configuration of a general microcomputer control circuit section is shown in FIG. In the figure, an instruction portion of the read data of the instruction word storage device 12 accessed by the address indicated by the program counter 11 is placed in the instruction register 13. The instruction register 13 and the state control register 14 that controls the instruction execution cycle are input to an instruction decoder 15, and the microcomputer is controlled by the output thereof.

In this device, the output 1a of the instruction decoder 15
1b controls the program counter 11 (increment, branch, etc.), and 1b controls the state control register 1.
4 control is performed. Further, 1c controls built-in registers, an arithmetic logic unit (hereinafter referred to as ALU), a data memory (hereinafter referred to as RAM), and the like.

By the way, the instruction decoder 15 is composed of a decoder section 16 and an encoder section 17 as shown in FIG. 2, and the control signal 2a consists of one output from the decoder section 16 and one output from the encoder section 17.

In the present invention, an instruction decoder circuit consisting of a decoder section (corresponding to AND logic) and an encoder section (corresponding to OR logic) is configured to consist of a main instruction decoder and a subordinate instruction decoder, thereby significantly reducing the circuit scale. The purpose is to provide a decoder circuit. The present invention will be described below along with examples. FIG. 3 shows an instruction decoder circuit according to one embodiment of the present invention. In the figure, the instruction decoder 15 shown in FIG. Part 3b of output
The output thereof is connected to the decode output of the main instruction decoder 18 by wired logic. Generally, the effective level of the control output 3c wired to the main instruction decoder 18 and the slave instruction decoder 19 is selected to be the LOW level. (In addition, in general logic circuits, when determining logical values by wired connections, the effective level is LOW).

Next, the present embodiment will be specifically explained using the instruction coding example shown in FIG. 4 and the configuration of registers and arithmetic section. First, in T1, instruction register 1
A value of 3 (00000000) is set, the A register and the X register are added, and the result is stored in the A register. At T2, a value (00000001) is set in the instruction register 13, and the logical product of the A register and the X register is taken and stored in the A register. Similarly, at T3, (00000010) is set, the exclusive OR of the A register and the X register is taken, and the result is stored in the A register. Also, in T4, (00000011) is set, and the A register and
The logical sum of the registers is taken and stored in the A register. Also, at T5, (00000100) is set, the logical sum of the A register and the Y register is taken, and the
Store in register. At T6, (00000101) is set, and the logical product of the A register and the negation of the Y register is taken and stored in the A register.

Figure 5 shows the 4th block in the register and ALU section.
Only the parts necessary to explain the instructions shown in the figure are shown. That is, the bus configuration is three buses 4a, 4b, and 4c. A register 20 is connected to bus 4b
It outputs data to and takes in data from the output bus 4c of the ALU 21. X register 22 is connected to bus 4a
It outputs data to and takes in data from the output bus 4c of the ALU 21. Y register 23 is connected to bus 4a
It outputs data to and takes in data from the output bus 4c of the ALU 21. The bus 4b is directly input to the ALU 21. The bus 4a is also input to the ALU 21 via a complement control unit 24 that takes one's complement.

The output of the complement control section 24 becomes the complement of the input when the CCOMP signal 4d is at a valid level (LOW level), and when it is at a HIGH level, the output remains the input value.

ALU21 performs binary addition, AND, exclusive OR, and OR of inputs using ALU control signal CALU1,
4e, CALU2, and 4f. Specify the calculation mode of CALU1 and CALU2 in the 6th
As shown in the figure.

In the instruction group shown in FIG. 4, T1, T2, T3 and T4 form one group. That is, in FIG. 5, the above instructions differ only in the mode of the ALU 21, and output the A register 20 to the bus 4b.
outputting the X register 22 to the bus 4a; and
Taking the output of the ALU 21 into the A register is the same. Therefore, the control signal common to T1 to T4 uses the control output section 3d dedicated to the main instruction decoder of the main instruction decoder 18 shown in FIG.
21 control signals CALU, 4e, CALU2, 4f are the control signals 4e, 4e, CALU 2, 4f from the main instruction decoder 18 to the ALU 21 in order to use the slave instruction decoder 19.
4f is invalidated and a control signal is sent to the slave instruction decoder 19.
Send CCNφ, CCN1, 3b.

Here, the control outputs 4e, 4 of the main instruction decoder 18
Disabling f means configuring the main instruction decoder 18 so that when the combined output of the main instruction decoder 18 and slave instruction decoder 19 is separated, the output becomes High level.

The slave instruction decoder 19 is CCNφ, CCN1, 3b
and the lower two bits iR1 and iRφ of the instruction register 13
is input, and the control mode of ALU21 is set to CALU.
2. Specified by CALU1.

Thus, for the instruction group T1 to T4, the main instruction decoder only needs to decode the upper six bits of the instruction register.

FIG. 9 is a block diagram showing the instruction decoder circuit of FIG. 3 in more detail, and the case where instructions T1 to T4 are added will be explained in more detail using FIG.

In the figure, 18a and 18b are the decoder section and encoder section of the main instruction decoder 18, respectively, and 19a and 19b are the subordinate instruction decoder 1, respectively.
These are the decoder section and the encoder section in 9. The instruction from the instruction register 13 is sent to the main instruction decoder 18
When the instruction is applied to the decoder section 18a, one output line corresponding to this instruction is selected. The encoder section 18b of the main command decoder 18 outputs a control signal corresponding to the command according to the selected output line.

When commands T1 to T4 are now added, the same output line of the decoder section 18a is selected for these commands, and a control signal 3d common to the commands T1 to T4 is outputted from the encoder section 18b. Furthermore, a control signal 3b is output from the encoder section 18b.
(CCN ₀ =0, CCN ₁ =0) is output and added to the decoder section 19a of the slave instruction decoder 19. The lower two bits (iR ₀ , iR ₁ ) of the instructions T1 to T4 are also added to this decoder section 19a. In the decoder section 19a, one of the output lines is selected based on the values of CCN ₀ , CCN ₁ , iR ₀ , and iR ₁ . That is,
Instruction T1 (iR ₀ = 0, iR ₁ = 0), instruction T2 (iR ₀ =
1, iR ₁ =0), instruction T3 (iR ₀ =0, iR ₁ =1),
The output line corresponding to command T4 (iR ₀ =1, iR ₁ =1) is selected. The encoder unit 19b of the slave instruction decoder 19 outputs control signals 4d, 4e, and 4f that are not common among the instruction groups T1 to T4 among the control signals corresponding to the instruction (for example, for instruction T1, CCOMP =H, CALU1=L,
CALU2=L) is output.

That is, the decoder section 18a of the main instruction decoder 18
In the present invention, four output lines, which were conventionally required for each instruction, can be reduced to one for four types of instructions T1 to T4. This reduces the area of the main instruction decoder.

Next, the cases of T5 and T6 of the instruction group shown in FIG. 4 will be explained. In the case of T5 and T6, the fourth
In the figure, the only difference is the mode of the ALU 21 and the complement control unit 24, and the A register 20 is connected to the bus 4b.
Outputting the Y register 23 to the bus 4a, and taking in the output of the ALU 21 to the A register are the same. So T5~T6
The common control signal is the main command decoder 18 in FIG.
The control output unit 3d dedicated to the main instruction decoder is used, and the control signals CALU, 4e, of the ALU 21 are
CALU2, 4f and complement control signal 4d are sent to main instruction decoder 1 in order to use slave instruction decoder 19.
ALU21 control signal CALU1, 4e from 8,
CALU2, 4f and complement control signal 4d are disabled, and control signals CCNφ, CCN are sent to the slave instruction decoder.
Send 1,3b.

The slave instruction decoder inputs CCNφ, CCN1, 3b and the lower two bits iR1 and iRφ of the instruction register, and receives the control signals of ALU21, CALU1, 4e,
Outputs CAL2, 4f and complement control signal 4d.

In this way, even in the instruction groups T5 and T6, the main instruction decoder only needs to decode the upper six bits of the instruction register.

FIG. 7 shows the contents of the slave instruction decoder in the cases T1 to T6 described above. In this figure 7, CCN
1, CCNφ is a control output from the main instruction decoder 18 to the slave instruction decoder 19. It is set to (00) for T1 to T4, and (01) for T5 and T6.
Moreover, when the slave instruction decoder 19 is not used, (11) is used. CCOMP, CALM2, CALM
1 is a control output signal from the slave instruction decoder.
These signals are controlled by the main instruction decoder 18 when the slave instruction decoder 19 is not used.
As is clear from FIG. 7, the slave instruction decoder includes a decoder section which inputs CCN1, CCNφ, iR1, and iRφ and outputs T1 to T6 and the main instruction decoder mode, and an output from this decoder section. It consists of an encoder section whose outputs are CCOMP, CALU2, and CALU1.

By employing the slave instruction decoder 19 described above, the slave instruction decoder control output 3b of the main instruction decoder 18 increases, but the number of slave instruction decoder inputs {(3a) + (3b)} is equal to the number of main instruction decoder inputs. In general, the instruction decoding section is much simpler, especially for microcomputers.
There is a great effect when it is made with LSi.

In the instruction group shown in Figure 4, T1 to T4 are operations on the A register and If we have the instruction group shown in Figure 5 and the Z register is connected to the bus 4a in Figure 5, the slave instruction decoder will also decode instructions T7, T8, T9, and T10 of the instruction group related to the Z register. The main instruction decoder only needs to decode the upper 6 bits (000010) of the instruction register 13. In this way, the microcomputer's instruction set includes the slave instruction decoder 1.
If one mode of 9 is available, it exists multiple times, allowing further reduction of the instruction decoder circuit 15. However, if the instruction decoding circuit of the present invention is used, the time it takes for the instruction decoder output to become stable will be the access time of the main instruction decoder + the access time of the slave instruction decoder. In the case of computers, etc., this drawback can be avoided.

In the above explanation, the case where there is a single slave instruction decoder is described, but the effect of the present invention is further expanded by providing a plurality of slave instruction decoders and grouping instruction groups.This is a design change. It's nothing more than that.

As described above, the instruction decoder circuit including the main instruction decoder and the slave instruction decoder according to the present invention can significantly reduce the circuit scale compared to the case where a single instruction decoder method is adopted. As a result, effects such as lowering manufacturing costs can also be obtained.

Further, according to the present invention, the code assignment of the instruction register input to the slave instruction decoder only needs to distinguish between ALU control modes. Generally, when designing instruction codes for a processor, restrictions on instruction code assignments from control structures etc. make the design extremely difficult, but according to the present invention, the degree of freedom in instruction code assignments is large. This makes the design easier. Further, it is possible to set a plurality of control modes as the control modes to be converted by the slave instruction decoder consisting of a decoder section and an encoder section.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microcomputer control circuit, FIG. 2 is a block diagram of a general instruction decoder circuit, FIG. 3 is a block diagram of an instruction decoder circuit according to an embodiment of the present invention, and FIG. 4 is an instruction coating. Figure 5 is a block diagram showing the detailed configuration of the main parts, Figure 6 is a diagram showing the operation mode of the ALU, Figure 7 is a diagram showing the contents of the slave instruction decoder, and Figure 8 is the instruction FIG. 9 is a block diagram showing details of the instruction decoder circuit of FIG. 3. 13...Instruction register, 18...Main instruction decoder, 19...Slave instruction decoder.

Claims (1)

[Claims] 1 In an instruction decoder circuit that generates control signals for a microcomputer configured on a semiconductor integrated circuit, a main circuit that includes as input all the outputs of the instruction register section that needs to be decoded due to the instruction structure, and that consists of a decoder section and an encoder section. The main instruction decoder and the slave instruction decoder are provided with an instruction decoder and a slave instruction decoder which takes as input some control signals from the main instruction decoder and a portion of the output of the instruction register section, and is composed of a decoder section and an encoder section. A mode in which control signal outputs for the same control target in the instruction decoder are connected and the main instruction decoder is assigned the generation of control signals for a group of instructions whose control signals are not common among each instruction; , by assigning the generation of the common control signal to the main instruction decoder for at least some instruction groups that have a part of their control signals in common. In this mode, the output line of the decoder section is shared, and the generation of control signals that are not common in the instruction group is assigned to the slave instruction decoder, and the output of the slave instruction decoder is controlled by some control signals from the main instruction decoder. An instruction decoder circuit characterized in that the instruction decoder circuit performs the above-mentioned mode switching.