JPS60134940A - Register selecting system of information processing device - Google Patents

Abstract

PURPOSE:To assign a specific register to every interrupt level without paying any attention to interrupt levels on a program by providing a means which converts contents of a register designating part of an instruction in accordance with the interrupt level. CONSTITUTION:Lower three bits in a part R of an instruction register 2 are outputted as a lower address of a general register 5 to a signal line 6, and upper one bit is inputted to an address converting circuit 4 through a signal line 7. A register 3 inputs contents of the interrupt level to the address converting circuit 4 through a signal line 8. Four kinds of interrupt level, 0-3 are provided, and the address converting circuit 4 performs prescribed conversion in accordance with the state ''1'' or ''0'' of the signal line 7 and the interrupt level of the signal line 8 and the upper address of the general register 5 to a signal line 9. The register 5 is divided to 5 blocks, and addresses in blocks are designated by the lower address of the signal line 6, and addresses of blocks are designated by the upper address of the signal line 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention J] The present invention relates to an information processing device, and more particularly to a general-purpose register selection method for each interrupt level in a microprocessor or the like.

BACKGROUND OF THE INVENTION As is well known, when an interrupt occurs in an information processing device, the process being executed is interrupted, the process related to the interrupt is executed, and when the process is completed, the process returns to the original process. Also, if an interrupt with a higher priority occurs while processing related to a certain interrupt is being executed, the interrupt processing that is currently being executed is interrupted and processing related to the newly generated interrupt is executed. The process related to the interrupted interrupt is restarted, and when it is finished, the process returns to normal processing.

By the way, in conventional microprocessors, etc., access to all general-purpose registers is allowed regardless of the interrupt level. Therefore, every time an interrupt occurs, the data on the general-purpose register is saved to the main memory, and when returning from the interrupt, the saved data is read from the main memory and reset to the general-purpose register. Since this work was mainly performed by a program, the structure of the program was complicated, and in some cases, the performance of the device using the microprocessor could be affected.

Also, depending on the microprocessor architecture,
There is also a method that uses a bush-and-pop stack without using general-purpose registers, but it has less flexibility than a method that uses randomly accessible general-purpose registers, and
It is necessary to manage stack overflow, etc.

[9! An object of the present invention is to provide a register selection method that allows Program-E to allocate a unique register for each interrupt level in a microprocessor or the like without being aware of the interrupt level. be.

[Summary of the Invention j A feature of the present invention is that a means is provided for converting the contents of the register specification section in an instruction in accordance with the interrupt level, so that even if the same register is specified in the instruction code, it is physically different. This allows you to select registers.

[Embodiments of the invention]

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a microprocessor, and its components related to the present invention include an instruction register 21, an interrupt level holding register 3. It has an address conversion circuit 4, a general-purpose register 5, and the like. It is assumed that the R part of the instruction register 2 specifies the address of the general-purpose register 5, and is composed of 4 pins I-.

The lower 3 bits of the R part of the instruction register 2 are output to the signal line 6 as the lower address of the general-purpose register 5, and the upper 1L
” is input to the address conversion circuit 4 via the signal line 7.Register 3 is a register that holds the interrupt level.
The contents are also input to the address conversion circuit 4 via the signal line 8. Here, it is assumed that the interrupt level has four levels, 0 to 3. The address conversion circuit 4 is connected to the l of the signal line 7.
], IZ" Q The conversion shown in FIG. 2 is performed according to the state of 11 and the interrupt level of signal line 8, and the upper address of general-purpose register 5 is output to signal line 9. General-purpose register 5 is divided into five blocks. One block consists of eight words (registers). 71 to 71 in the block in the general-purpose register 5 are indicated by the lower address of the signal line 6, and the address of the block is indicated by the upper address of the signal line 9. shown.

For example, the upper 1 bit of the R part of instruction register 2 is "0".
In the case of I+, the output line 9 of the address conversion circuit 4 becomes rOJ regardless of the interrupt level, and the area of the general-purpose register 5 accessed by the instruction always becomes block O. On the other hand, if the j-th bit of the R section of the instruction register 2 is 'bi', the output line 9 of the address conversion circuit 4 will be from ``1'' to ``4'' corresponding to the 1 interrupt level 0 to 3, and the instruction Even if you specify the same general-purpose register address, general-purpose register 5
As for the area, different areas of blocks 1 to 5 are accessed. - Therefore, by assigning data specific to each interrupt level 0 to 3 to blocks 1 to 4, the program can create a unique block in the general-purpose register 5 for each interrupt level without being aware of the interrupt level. Since the data in the general-purpose register 5 must be saved to the main memory (not shown) each time an interrupt occurs, the data in the general-purpose register 5 must be saved in the main memory (not shown). Data to be used can also be exchanged.

FIG. 3 is a block diagram of another embodiment of the present invention, in which the same parts as in FIG. 1 are designated by the same reference numerals.

The difference from FIG. 1 is that the R part of the instruction register 2 is 5 bits wide, and the upper 2 bits enter the address conversion circuit 4 via the signal line 7 and undergo rear address conversion, and the address conversion circuit 4 is connected to the register file. It has a structure, and its contents can be rewritten at will. When the command code C of the instruction register 2 is a register file setting command, the decode output line 12 of the decoder 10 becomes '1'' and the data is set to the address conversion circuit 4 which has a register file configuration. The data of the operand of the instruction register 2 is written through the data line 11.The address conversion circuit 4 converts the interrupt level of the signal line 8 into the upper address and the data of the operand of the Bit data as lower address.

The data at the corresponding address in the register file is output to the signal line 9, and is set as the upper 71-res (block address) of the general-purpose register 5. Lower ato I of general-purpose register 5
The address (intra-block address) is indicated by the lower three bits of the R section of the instruction register 2 through the signal line 6.

Assume now that the data set in the address conversion circuit 4 by the program is as shown in FIG. In this case, the blocks of general-purpose registers 5 allocated to each interrupt level are substantially the same as in FIG. 2. That is, in this case, the most significant bit of the R part numbered in the instruction register 2 has meaning only when it is II OII. On the other hand, when the present microprocessor 1 is used for applications that do not use interrupts of multiple levels, the data shown in the table of FIG. 5 is set in the address conversion circuit 4. In this case, microprocessor 1
Suppose that is always at interrupt level 0.

All 32 word addresses shown in the R section of the instruction register 2 can be used for instructions. At this time, 1 interrupt level is 0
For general purpose register 5, blocks 0 to 3 are used.

In the embodiments shown in FIGS. 1 and 3, the microprocessor 1 is used, but it goes without saying that the present invention can be applied to systems other than microprocessors.

〔Effect of the invention〕

As is clear from the above description, the following effects can be obtained with the present invention.

(1) Due to the instruction code, a unique general-purpose register can be used for each interrupt level using the same address.

(2) Depending on the purpose, the size and address of the general-purpose register area used for each interrupt level can be changed.

(3) Due to the reason in (1), it is no longer necessary to save data in a general-purpose register every time one interrupt occurs, which simplifies the structure of the program.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a diagram showing the logical operation of the 71-less conversion circuit in FIG. 1, and FIG. 3 is a block diagram of another embodiment of the present invention. 4 and 5 are diagrams showing examples of data set in the address conversion circuit in FIG. 3. l...Microprocessor, 2...Instruction register. 3... Interrupt level holding register 54... Address conversion circuit, 5... General purpose register. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] (1) In an information processing device that is equipped with a plurality of registers and selects a desired register based on the contents of a register specification section in an instruction, the contents of the register specification section in the instruction and a signal indicating an interrupt level are selected in six ways. A register selection method characterized in that a conversion means is provided for converting the contents of the register specifying section in accordance with the interrupt level, and a register is selected based on the conversion output of the selection means. (2) The register selection method according to claim 1, wherein the conversion table of the conversion means is arbitrarily changed by a command.