JPH0424852A - Multi-port access system - Google Patents

Abstract

PURPOSE:To omit an exclusive port processing routine which is needed for each port and for the high speed processing by using the contents of a port register not the I/O address included in the access information to select the ports. CONSTITUTION:A decoder 16 decodes the port designation data set to a port register 14 when the contents stored in an I/O address field led by the decoder 16 are identical with a common port address. Then the decoder 16 selects the ports 11-i (i = 1-n) to which the value shown by the port designation data is assigned and generates and outputs the port selection signals 17-i. Thus the port 11-i are selected and start the operations shown by the contents of a function designation field included in the address information led via a receiver 15. If an access is desired to another following port, it is just required to set the port designation data to the register 14 and to give a common access to each port. Thus it is not required to prepare a port processing routine that is needed for each port and for the high speed processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a multiport access method suitable for accessing at least one of a plurality of ports.

(Prior art) Conventionally, in order to control multiple ports, an input/output address (I/O address) was assigned to each port at the same level as the input/output register (I/O register), and the A method of specifying a port using an I/O address field provided in address information in the same way as an I/O register was applied. In this method, port selection is
This is performed by an address decoder decoding the contents of the I/O address field in the address information.

(Problem to be solved by the invention) In the conventional port selection method described above, during programming,
It includes a process that determines the port to be accessed and rewrites the port processing routine for the determined port (for example, rewrites the contents of the I10 address field to specify the port to be accessed). There was a problem with slowdown. It is also known to prepare a program for each port in order to increase the processing speed, but this has the problem of increasing the scale of the program and requiring a large capacity program memory.

This invention has been made in view of the above circumstances, and its purpose is to provide a multi-purpose multi-port system that can quickly control access to at least one of multiple ports without preparing a port processing routine for each port. The purpose is to provide a port access method.

[Structure of the Invention (Means for Solving the Problems) This invention provides a port register into which port designation data for designating at least one port to be accessed among a plurality of ports is loaded by an input/output write instruction. , a decoder that decodes the contents of this port register and selects the port specified by the register,
1 to select the port according to the contents of the port register.
It is characterized by this.

(Operation) According to the above configuration, when port access specification is performed after setting the port specification data that specifies the port register (the ability to access which of the plurality of ports),
Even if the port to be accessed is not specified in this port access specification, that is, even if a common port access specification is used, the port specification data set in one port register can be correctly selected simply by decoding the port specification data. (can.

(Embodiment) FIG. 1 is a block diagram of a program around a multi-boat access mechanism according to an embodiment of the present invention.

In the figure, 11-1.1l-2-11-n are ports, for example, serial input/output interfaces (SIO) having the same communication interface function. port 1
Each of 1-1 to 11-n is assigned a unique value, and is designated by port designation data, which will be described later. 12 is a data bus used for transferring various data, and 13 is an address bus 13 used for transferring address information. 14 is a register (hereinafter referred to as a port register) into which port designation data for specifying one port to be accessed among the ports 11-1 to 11-n is loaded via the data bus 12, and 15 is an address bus. 16 is a register for taking in the address information transferred via the receiver 13. When the address information taken in by the receiver 15 is information specifying port access, the contents of the port register 14 (port specification 1 of port selection signals 17-1 to 17-n for decoding data) and selecting ports 11-1 to 11-n.
This is a decoder that makes one true.

Next, the operation of the configuration shown in FIG. 1 will be explained.

First, an I10 write instruction (input/output write instruction) is issued to load (write) port specification data from the CPU (not shown) to the port register 14 (when issued, the port specified directly or indirectly by the same instruction is Specified data is output to the data node 12 and loaded into the port register 14. This port specified data is outputted to the data node 12 and loaded into the port register 14.
-n indicates one of the values numbered III, and is generated, for example, from the result of determining the port to be accessed.

Next, an input/output access command with address information as shown in FIG. 2 is issued in order to access any of the ports 11-1 to 11-n from the CPU. The I10 address field of the information contains an I10 address numbered 1-111 common to ports 11-1 to 11-n (hereinafter referred to as common port address).
is set. This address information is address bus 1
3, the register is transferred to /<15+. Receiver 1
5 takes in the address information transferred via the address node 13. The portion of the address information taken in by register 7<15, excluding the I10 address field, is commonly led to ports 11-1 to 11-n. Also, the I10 address field portion of the address information is guided to the decoder 16.

If the content of the I10 address field led to the decoder 16 is a common port address, the decoder 16 decodes the port designation data set in the port register 14 and assigns the value indicated by the port designation data. A port selection signal 17-1 for selecting the selected port If-f (i is one of 1 to n) is generated and output. As a result, port 11-1 is selected. The port 11-1 selected by the port selection signal 17-j from the decoder 16 starts the operation indicated by the contents of the function designation field in the address information led through the receiver 15. If it is desired to access another port next time, it is sufficient to set the port designation data in the port register 14 described above and perform a common port access to each port. However, if you access the same port continuously,
Port specification data setting processing becomes unnecessary.

In the above embodiment, the ports 11-1 to 11-n are designated by the port designation data set in the port register 14.
Although the description has been made assuming that one of them is designated, the invention is not limited to this. For example, by assigning each bit of port designation data to ports 11-1 to 11-n,
It becomes possible to simultaneously designate a plurality of ports using the port register 14 and set up the plurality of ports simultaneously using port access designation address information having a common port address.

Further, in the embodiment described above, port access for SIO has been described, but the present invention is not limited to 510, but is particularly effective for port access for I10 devices having the same functions.

[Effects of the Invention] As detailed above, according to the present invention, there is provided a port register in which port designation data is set by an input/output write command, and a decoder that decodes the contents of this port register and selects a port. By adopting a configuration in which port selection is performed based on the contents of the port register rather than the I10 address in the address information, there is no need to prepare a dedicated port processing routine for each port for high-speed processing, and the same processing routine can be shared. Therefore, it is possible to realize high-speed processing while simplifying and downsizing the program.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the peripheral area of a multiport access mechanism according to an embodiment of the present invention, FIG. 2 is a diagram showing the format of address information having an I10 address field, and FIG. 3 is a diagram showing the program structure in the conventional method. It is a diagram. 11-1 to 11-n...Port, 12...Data bus, 13...Address bus, 14...Port register, 15...Receiver, 16...Decoder. Applicant's agent Patent attorney Takehiko Suzue

Claims (2)

[Claims] (1) At least one of multiple ports to be accessed
The device comprises a port register into which port designation data for designating one port is loaded by an input/output write instruction, and a decoder that decodes the contents of this port register and selects the port designated by the register. A multi-port access method characterized by selecting a port according to the contents of a port register. (2) A common specific input/output address is assigned to the plurality of ports, and the decoder is given address information for port access that has an input/output address field in which the specific input/output address is set. In case,
2. The multi-port access method according to claim 1, wherein port selection is performed in accordance with the contents of said port register.