JPS6186859A - Bus selector - Google Patents

Abstract

PURPOSE:To improve the performance of a central processor as well as the using efficiency of a bus by using the bus numbers stored in a main memory and connected with each interface device. CONSTITUTION:A bus number corresponding to an identification number is stored as the data in an area used exclusively by the hardware of a main memory 1. Then all identification numbers are sent to all buses 20-22 in a system rise mode for check of the connecting relation between a bus and an interface device having an identification number. The bus number of the interface device having an identification number is read out of the memory 1 via a data line 11. A control circuit 2 sets the number given from the line 11 to a bus number feed 31 of an interface device register 3 and supplied to a bus selection circuit 4. Then the output of an identification number data line 10 is selected for each bus and sent to a bus as a command of the interface device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a noise control method used in a data processing device. Especially regarding the bus selection method.

[Conventional technology]

Conventionally, in a central processing unit that can connect multiple buses, interface devices are selected for each north one by one as a bus selection means, and when the selected bus does not have the desired interface device, the next bus number is selected. A method of sequentially accessing the files has been used.

[Problem that the invention seeks to solve]

However, in the above method, when selecting the interface device connected to the last bus among the buses to be selected, unnecessary interface device selection instructions are issued to all buses, and the device selection time is wasted. This causes a decrease in the performance of the central processing unit. Also, sending an interface device selection instruction to each bus means that each bus will spend a certain amount of time on that instruction. , which had the disadvantage that other interface devices were prevented from using the bus during that time.

The present invention solves the above-mentioned problems, and aims to provide a selection device that improves the performance of a central processing unit and the efficiency of using a bus.

[Means for Solving the Problems] The present invention has a plurality of buses connected through a bus selection circuit, and one of the buses is selected by an identification number given to an interface device connected to the plurality of buses. In a bus selection device for a central processing unit having biased selection means, an area for storing a corresponding bus number is provided on an address based on the identification number of a main storage device connected to the central processing unit, and the selection means is provided with an area for storing a corresponding bus number. is characterized in that it includes means for reading the contents of the address according to the identification number and selecting one of the buses according to the contents.

[Effect]

The identification number of the interface device is used as an address in the main device 1a, and the bus number to which the interface device is connected is stored. By giving an identification number corresponding to the interface device to be connected, the data bus number can be determined, and the desired interface device can be quickly selected.

〔Example〕

Next, the present invention will be described in detail with reference to the accompanying drawings.

An example circuit of the present invention is shown in FIG. This figure is a circuit diagram showing the connection portion of the central processing unit to the bus. Main story 1!
The output of device 1 is input to bus number field 31 of interface device register 3. One output of the control circuit 2 is input to the main storage device 1, and the other output is
Enter the above bus number field 31. The output of the bus number field 31 is input to the main storage device 1 and also to the bus selection circuit 4. The output of the identification number field 32 of the interface device register 3 is inputted to the bus selection circuit 4 and also inputted to the main storage device 1. Bus selection circuit 40 three outputs are bus 20 and bus 21
and bus 22, respectively, and are coupled to an interface device (not shown).

The central processing unit selects and instructs the interface device by sending an interface device command including an interface device identification number to the interface device connected to the bus. In FIG. 1, interface device register 3 includes a bus number field 31 and an interface device identification number field 32. The signal on the interface device identification number data line 10 becomes an input signal to the node selection circuit 4 and the main memory device 1. The main entry (?HHI3) is used as address information for the stored bus number data, and is used by the bus selection circuit 4 as interface device identification number information.

Main entry
By sending the information to 22, it is possible to know which interface device with which identification number is connected to which bus. Additionally, in a fixed system, the bus number can be stored as data at the beginning. The identification number field data line 10 serves as an address for the bus number data of the hardware exclusive use area, and the bus number of the interface device that is 1h apart from the identification number is read from the main memory via the data line 11.

Control circuit 2 sets the number from data line 11 in bus number field 31 of interface device register 3. The bus number I3 in the bus number field 31 is input to the bus selection circuit 4, which selects the identification number data line 10 output as one of each bus and sends it to the bus as an interface device command. FIG. 2 is a detailed circuit diagram of the bus selection circuit 4. The identification number data yIclo and the output 45 of the decoding circuit 41 are each input to a plurality of AND circuits 4.
2a to the bus 20. The identification number data line IO and the output 44 of the decoding circuit 41 are respectively outputted to the bus 21 via a plurality of other AND circuits 42b. Further, the identification number data line 10 and the output 43 of the decoding circuit 41 are each output to the bus 22 via a plurality of separate AND circuits 42c. The bus number input line 13 is output by the decoding circuit 41 as each bus selection signal from circuit outputs 43 to 43.
45. The identification number data line 10 output is
The decode circuit output signals 43 to 45 selected by the AND circuit group 42 (a, b, c) are output to designated buses 20 to 22.

When the system is started up, the correspondence between the bus number and the identification number is investigated, and the bus number data is written into the main storage device 1. This operation will be further explained. The control circuit 2 stores the initial values of the identification number and the bus number in the interface device register 3. This may be replaced by a reset operation.

As described above, if an interface device command is sent and there is no corresponding interface device, the next bus number is set in the bus number field 31 and the interface device command is sent again. If an interface device is selected, the bus number field bus number line 13 output is used as the identification number field data'
It is stored in the data field of the main storage device 1 addressed by the frfAIO output, and the next identification number is set in the identification number field 32. By checking all the identification numbers through the above procedure, the bus number to which the interface device is connected is determined.

〔Effect of the invention〕

As explained above, the present invention eliminates unnecessary access to the bus and improves the throughput of the central processing and interface devices by using the connected bus number of each interface device stored in the main memory. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. FIG. 2 is a detailed block diagram of the bus selection circuit shown in FIG. 1. DESCRIPTION OF SYMBOLS 1... Main register/billion device, 2... Control circuit, 3... Interface device register, 4... Bus selection circuit,
10...Identification number data line, 13...Bus number line,
31... Bus number field, 32... Identification number field, 41... Decode circuit, 42... AND circuit, 43 to 45... Single decode output.

Claims (1)

[Claims] (1) A bus for a central processing unit in which a plurality of buses are connected via a bus selection circuit and includes means for selecting one of the buses based on an identification number given to an interface device connected to the plurality of buses. In the selection device, an area for storing a corresponding bus number is provided on an address based on the identification number of the main storage device connected to the central processing unit, and the selection means selects the contents of the address according to the identification number. 1. A bus selection device comprising means for reading out a bus and selecting one of the buses according to the contents thereof.