JPS5537648A - Instruction decoder circuit - Google Patents
Instruction decoder circuitInfo
- Publication number
- JPS5537648A JPS5537648A JP11042278A JP11042278A JPS5537648A JP S5537648 A JPS5537648 A JP S5537648A JP 11042278 A JP11042278 A JP 11042278A JP 11042278 A JP11042278 A JP 11042278A JP S5537648 A JPS5537648 A JP S5537648A
- Authority
- JP
- Japan
- Prior art keywords
- decoder
- outputs
- instruction
- register
- master
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Executing Machine-Instructions (AREA)
Abstract
PURPOSE: To reduce the number of decoder signals lines to an encoder part by providing a master instruction decoder to which outputs of an instruction register are all inputted and a slave instruction decoder to which outputs of the master decoder and part of outputs of the instruction register are inputted.
CONSTITUTION: An instruction decoder is divided into master instruction decoder 18 and slave instruction decoder 19 and decoder 18 is supplied with outputs of register 13 and atate control register 14. Decoder 19 is supplied with part 3a of outputs of register 13 and part 3b of outputs of decoder 18, and its outputs are led out together with decoding outputs 3c of decoder 18 by wired logic connections. In the arithmetic mode of a logical operation part, a common control signal uses control output part 3d only for the master instruction decoder of decoder 18 to hold control output 3c at level "H", thereby making a disconnection from decoder 19. Decoder 18 is supplied with outputs CCN0 and CCN1 of decoder 18 and lower two bits of instruction register 13 to assign the control mode of the logical operation part. Consequently, the number of signal lines of the instruction decoder part decreases and simplification is realized.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11042278A JPS5537648A (en) | 1978-09-07 | 1978-09-07 | Instruction decoder circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11042278A JPS5537648A (en) | 1978-09-07 | 1978-09-07 | Instruction decoder circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5537648A true JPS5537648A (en) | 1980-03-15 |
JPS6246891B2 JPS6246891B2 (en) | 1987-10-05 |
Family
ID=14535351
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11042278A Granted JPS5537648A (en) | 1978-09-07 | 1978-09-07 | Instruction decoder circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5537648A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS592146A (en) * | 1982-06-29 | 1984-01-07 | Fujitsu Ltd | Microprogram control device |
CN102841776A (en) * | 1994-12-02 | 2012-12-26 | 英特尔公司 | Microprocessor capable of compressing composite operation number |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02253082A (en) * | 1989-03-24 | 1990-10-11 | Tokai Rubber Ind Ltd | Connector |
-
1978
- 1978-09-07 JP JP11042278A patent/JPS5537648A/en active Granted
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS592146A (en) * | 1982-06-29 | 1984-01-07 | Fujitsu Ltd | Microprogram control device |
JPH0517574B2 (en) * | 1982-06-29 | 1993-03-09 | Fujitsu Ltd | |
CN102841776A (en) * | 1994-12-02 | 2012-12-26 | 英特尔公司 | Microprocessor capable of compressing composite operation number |
US9015453B2 (en) | 1994-12-02 | 2015-04-21 | Intel Corporation | Packing odd bytes from two source registers of packed data |
US9116687B2 (en) | 1994-12-02 | 2015-08-25 | Intel Corporation | Packing in destination register half of each element with saturation from two source packed data registers |
US9141387B2 (en) | 1994-12-02 | 2015-09-22 | Intel Corporation | Processor executing unpack and pack instructions specifying two source packed data operands and saturation |
US9182983B2 (en) | 1994-12-02 | 2015-11-10 | Intel Corporation | Executing unpack instruction and pack instruction with saturation on packed data elements from two source operand registers |
US9223572B2 (en) | 1994-12-02 | 2015-12-29 | Intel Corporation | Interleaving half of packed data elements of size specified in instruction and stored in two source registers |
US9361100B2 (en) | 1994-12-02 | 2016-06-07 | Intel Corporation | Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements |
US9389858B2 (en) | 1994-12-02 | 2016-07-12 | Intel Corporation | Orderly storing of corresponding packed bytes from first and second source registers in result register |
Also Published As
Publication number | Publication date |
---|---|
JPS6246891B2 (en) | 1987-10-05 |
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