JPS55121566A - Information processor - Google Patents

Information processor

Info

Publication number
JPS55121566A
JPS55121566A JP2773479A JP2773479A JPS55121566A JP S55121566 A JPS55121566 A JP S55121566A JP 2773479 A JP2773479 A JP 2773479A JP 2773479 A JP2773479 A JP 2773479A JP S55121566 A JPS55121566 A JP S55121566A
Authority
JP
Japan
Prior art keywords
stop
subprocessors
subprocessor
transfer means
stop signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2773479A
Other languages
Japanese (ja)
Inventor
Masahiko Kida
Osamu Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2773479A priority Critical patent/JPS55121566A/en
Publication of JPS55121566A publication Critical patent/JPS55121566A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE: To simplify the investigation of cause when linkage operation among processors is debugged and a fault occurs, by making it possible to stop other random subprocessors at the same time under the stop condition of a random processor.
CONSTITUTION: Subprocessors 1, 2 and 3 operate independently one another at a usual time. Subprocessors 1, 2 and 3, having stop control registers 4, 5 and 6 respectively, are mutually connected by stop signal transfer means 10. Further, respective processors are provided with stop control registers and stop signal generators 7, 8 and 9 which generate a stop condition signal under the condition given by the above-mentioned stop signal transfer means. Now, when subprocessor 1 is to stop, the stop signal of subprocessor 1 is transferred to subprocessors 2 and 3 via stop signal transfer means 10, so that subprocessors 2 and 3 will stop simultaneously with subprocessor 1.
COPYRIGHT: (C)1980,JPO&Japio
JP2773479A 1979-03-12 1979-03-12 Information processor Pending JPS55121566A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2773479A JPS55121566A (en) 1979-03-12 1979-03-12 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2773479A JPS55121566A (en) 1979-03-12 1979-03-12 Information processor

Publications (1)

Publication Number Publication Date
JPS55121566A true JPS55121566A (en) 1980-09-18

Family

ID=12229246

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2773479A Pending JPS55121566A (en) 1979-03-12 1979-03-12 Information processor

Country Status (1)

Country Link
JP (1) JPS55121566A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57130131A (en) * 1981-02-03 1982-08-12 Nippon Denso Co Ltd Multiple computer device
JPS57209558A (en) * 1981-06-19 1982-12-22 Hitachi Ltd Emergency information system between processors
JPS588368A (en) * 1981-07-06 1983-01-18 Nec Corp Multiprocessor system
JPS5814204A (en) * 1981-07-20 1983-01-27 Hitachi Ltd Microcomputer controller
JPH03179538A (en) * 1989-12-08 1991-08-05 Hitachi Ltd Data processing system
JP2003162426A (en) * 2001-11-28 2003-06-06 Hitachi Ltd Computer system with cooperative debug circuit for multiple cpu and debug method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54136153A (en) * 1978-04-13 1979-10-23 Nec Corp Multiple processor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54136153A (en) * 1978-04-13 1979-10-23 Nec Corp Multiple processor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57130131A (en) * 1981-02-03 1982-08-12 Nippon Denso Co Ltd Multiple computer device
JPS57209558A (en) * 1981-06-19 1982-12-22 Hitachi Ltd Emergency information system between processors
JPS588368A (en) * 1981-07-06 1983-01-18 Nec Corp Multiprocessor system
JPS5814204A (en) * 1981-07-20 1983-01-27 Hitachi Ltd Microcomputer controller
JPH0413738B2 (en) * 1981-07-20 1992-03-10 Hitachi Ltd
JPH03179538A (en) * 1989-12-08 1991-08-05 Hitachi Ltd Data processing system
JP2003162426A (en) * 2001-11-28 2003-06-06 Hitachi Ltd Computer system with cooperative debug circuit for multiple cpu and debug method

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