JPS5543682A - Input/output unit control system - Google Patents

Input/output unit control system

Info

Publication number
JPS5543682A
JPS5543682A JP11714778A JP11714778A JPS5543682A JP S5543682 A JPS5543682 A JP S5543682A JP 11714778 A JP11714778 A JP 11714778A JP 11714778 A JP11714778 A JP 11714778A JP S5543682 A JPS5543682 A JP S5543682A
Authority
JP
Japan
Prior art keywords
input
units
output unit
processor
faulty
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11714778A
Other languages
Japanese (ja)
Other versions
JPS5824812B2 (en
Inventor
Akiji Hasegawa
Yasuhiko Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53117147A priority Critical patent/JPS5824812B2/en
Publication of JPS5543682A publication Critical patent/JPS5543682A/en
Publication of JPS5824812B2 publication Critical patent/JPS5824812B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To give the ineffective process by informing the input of the data containing an error to the processor via the input/output unit with isolation of the input/output unit, thus realizing a partial operation through the nondefective input/ output unit.
CONSTITUTION: Input/output units 4-1W4-n are connected to processor 2 via common buses 5W8. And in case no answer is given from units 4-1W4-n within the time set previously, one-shot multi 10 is actuated to produce the puseudo signal through OR gate 12 to return it to processor 2. With this pseudo signal, processor 2 confirms the erroneous data of faulty units 4-1W4-n and then carryes out the ineffective process via the interruption of OR gate 11. Furthermore, if faulty units 4-1W4-n are mounted, the faulty unit is isolated by switch 13 which sets the connection and isolation of units 4-1W4-n via timing control part 15. Thus only the nondefective units are connected with display of the fault on display unit 17.
COPYRIGHT: (C)1980,JPO&Japio
JP53117147A 1978-09-22 1978-09-22 I/O device management method Expired JPS5824812B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53117147A JPS5824812B2 (en) 1978-09-22 1978-09-22 I/O device management method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53117147A JPS5824812B2 (en) 1978-09-22 1978-09-22 I/O device management method

Publications (2)

Publication Number Publication Date
JPS5543682A true JPS5543682A (en) 1980-03-27
JPS5824812B2 JPS5824812B2 (en) 1983-05-24

Family

ID=14704618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53117147A Expired JPS5824812B2 (en) 1978-09-22 1978-09-22 I/O device management method

Country Status (1)

Country Link
JP (1) JPS5824812B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60217402A (en) * 1984-04-11 1985-10-31 Matsushita Electric Works Ltd Sequencer
JPS61296436A (en) * 1985-06-25 1986-12-27 Sanyo Electric Co Ltd Electronic apparatus
JPS6238950A (en) * 1985-08-13 1987-02-19 Nec Corp System for checking additional function of information processing peripheral unit
JPS63282865A (en) * 1987-05-15 1988-11-18 Nec Corp Input/output circuit
JPS6468858A (en) * 1987-09-09 1989-03-14 Nec Corp Microprocessor peripheral circuit
JPH0277752U (en) * 1988-11-29 1990-06-14
US7243257B2 (en) 2002-05-14 2007-07-10 Nec Corporation Computer system for preventing inter-node fault propagation

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018131550A1 (en) 2017-01-13 2018-07-19 日本電気株式会社 Connection management unit and connection management method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4938531A (en) * 1972-08-09 1974-04-10
JPS4975238A (en) * 1972-11-22 1974-07-19
JPS5016445A (en) * 1973-06-11 1975-02-21
JPS5140045A (en) * 1974-10-02 1976-04-03 Hitachi Ltd Seigyosochino eraajohoshitsuryokuhyojihoshiki
JPS52107741A (en) * 1976-03-08 1977-09-09 Hitachi Ltd Peripheral control unit
JPS5339018A (en) * 1976-09-22 1978-04-10 Nec Corp Detection control device for input spurious code

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4938531A (en) * 1972-08-09 1974-04-10
JPS4975238A (en) * 1972-11-22 1974-07-19
JPS5016445A (en) * 1973-06-11 1975-02-21
JPS5140045A (en) * 1974-10-02 1976-04-03 Hitachi Ltd Seigyosochino eraajohoshitsuryokuhyojihoshiki
JPS52107741A (en) * 1976-03-08 1977-09-09 Hitachi Ltd Peripheral control unit
JPS5339018A (en) * 1976-09-22 1978-04-10 Nec Corp Detection control device for input spurious code

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60217402A (en) * 1984-04-11 1985-10-31 Matsushita Electric Works Ltd Sequencer
JPS61296436A (en) * 1985-06-25 1986-12-27 Sanyo Electric Co Ltd Electronic apparatus
JPS6238950A (en) * 1985-08-13 1987-02-19 Nec Corp System for checking additional function of information processing peripheral unit
JPS63282865A (en) * 1987-05-15 1988-11-18 Nec Corp Input/output circuit
JPS6468858A (en) * 1987-09-09 1989-03-14 Nec Corp Microprocessor peripheral circuit
JPH0277752U (en) * 1988-11-29 1990-06-14
JPH0530197Y2 (en) * 1988-11-29 1993-08-02
US7243257B2 (en) 2002-05-14 2007-07-10 Nec Corporation Computer system for preventing inter-node fault propagation

Also Published As

Publication number Publication date
JPS5824812B2 (en) 1983-05-24

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